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Safeen Huda

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

10

Venues

8

Active years

2009–2026

Best venue rank

A*

Where they publish

Papers

10 indexed papers, newest first.

YearVenueTitleAuthors
2026AAAIHALO: Hardware-Aware Quantization with Low Critical-Path-Delay Weights for LLM Acceleration.Rohan Juneja, Shivam Aggarwal, Safeen Huda, Tulika Mitra, Li-Shiuan Peh
2024EMNLPShadowLLM: Predictor-based Contextual Sparsity for Large Language Models.Yash Akhauri, Ahmed F. AbouElhamayed, Jordan Dotzel, Zhiru Zhang, Alexander M. Rush, Safeen Huda, Mohamed S. Abdelfattah
2024NSDIResiliency at Scale: Managing Google's TPUv4 Machine Learning Supercomputer.Yazhou Zu, Alireza Ghaffarkhah, Hoang-Vu Dang, Brian Towles, Steven Hand, Safeen Huda, Adekunle Bello, Alexander Kolbasov, Arash Rezaei, Dayou Du, Steve Lacy, Hang Wang, Aaron Wisner, Chris Lewis, Henri Bahini
2022ASPLOSA full-stack search technique for domain optimized deep learning accelerators.Dan Zhang, Safeen Huda, Ebrahim M. Songhori, Kartik Prabhu, Quoc V. Le, Anna Goldie, Azalia Mirhoseini
2022DATELearning to Design Accurate Deep Learning Accelerators with Inaccurate Multipliers.Paras Jain, Safeen Huda, Martin Maas, Joseph E. Gonzalez, Ion Stoica, Azalia Mirhoseini
2016FPGATowards PVT-Tolerant Glitch-Free Operation in FPGAs.Safeen Huda, Jason Helge Anderson
2014FCCMOn Hard Adders and Carry Chains in FPGAs.Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
2014FPGAOptimizing effective interconnect capacitance for FPGA power reduction.Safeen Huda, Jason Helge Anderson, Hirotaka Tamura
2013FPLCharge recycling for power reduction in FPGA interconnect.Safeen Huda, Jason Helge Anderson, Hirotaka Tamura
2009FPLClock gating architectures for FPGA power reduction.Safeen Huda, Muntasir Mallick, Jason Helge Anderson