Salvador Manich
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
12
Venues
6
Active years
1996–2024
Best venue rank
B
Where they publish
Papers
12 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | IOLTS | On the Fine Tuning of RRAM Resistance Under Variability Using Current Pulses at SET. | Vahab Mahboubi, . Gmez, Antonio Calomarde, Daniel Arum, R. Rodrguez, Salvador Manich |
| 2014 | ETS | Interleaved scrambling technique: A novel low-power security layer for cache memories. | Madalin Neagu, Liviu Miclea, Salvador Manich |
| 2013 | ITC | Differential scan-path: A novel solution for secure design-for-testability. | Salvador Manich, Markus S. Wamser, Oscar M. Guillen, Georg Sigl |
| 2010 | ETS | Design and implementation of Automatic Test Equipment IP module. | S. Fransi, G. L. Farre, L. Garcia-Deiros, Salvador Manich |
| 2004 | VTS | BIST Technique by Equally Spaced Test Vector Sequences. | Salvador Manich, L. Garca, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodrguez-Montas, Joan Figueras |
| 2003 | ETS | On the selection of efficient arithmetic additive test pattern generators [logic test]. | Salvador Manich, L. Garca, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodrguez-Montas, Joan Figueras |
| 2002 | ITC | RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. | Marcelino B. Santos, Isabel C. Teixeira, Joo Paulo Teixeira, Salvador Manich, Rosa Rodrguez-Montas, Joan Figueras |
| 1999 | ETS | Low power BIST by filtering non-detecting vectors. | Salvador Manich, A. Gabarr, M. Lopez, Joan Figueras, Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch, Joo Paulo Teixeira, Marcelino B. Santos |
| 1999 | ISCAS | Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. | Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, Joo Paulo Teixeira, Marcelino B. Santos |
| 1997 | DATE | Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. | Salvador Manich, Joan Figueras |
| 1996 | DATE | Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations. | Michael Nicolaidis, Salvador Manich, Joan Figueras |
| 1996 | VTS | Enhancing realistic fault secureness in parity prediction array arithmetic operators by I | Salvador Manich, Michael Nicolaidis, Joan Figueras |