| 2021 | ASPDAC | HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks. | Soowang Park, Jae-Won Nam, Sandeep K. Gupta |
| 2020 | VTS | Aging-resilient SRAM design: an end-to-end framework. | Xuan Zuo, Sandeep K. Gupta |
| 2019 | VTS | Cache Design for Yield-per-Area Maximization: Switchable Spare Columns with Disabling (SSC-Disable). | Soowang Park, Sandeep K. Gupta |
| 2019 | VTS | A New Method for Software Test Data Generation Inspired by D-algorithm. | Jianwei Zhang, Sandeep K. Gupta, William G. J. Halfond |
| 2017 | VTS | Asymmetric sizing: An effective design approach for SRAM cells against BTI aging. | Xuan Zuo, Sandeep K. Gupta |
| 2016 | VTS | Using hardware testing approaches to improve software testing: Undetectable mutant identification. | Jianwei Zhang, Sandeep K. Gupta |
| 2016 | VTS | SRAM yield-per-area optimization under spatially-correlated process variation. | Jizhe Zhang, Sandeep K. Gupta |
| 2016 | VTS | Process variation oriented delay testing of SRAMs. | Xuan Zuo, Sandeep K. Gupta |
| 2015 | VTS | PPB: Partially-working processors binning for maximizing wafer utilization. | Da Cheng, Sandeep K. Gupta |
| 2015 | VTS | A multi-layered methodology for defect-tolerance of datapath modules in processors. | Hsunwei Hsiung, Sandeep K. Gupta |
| 2014 | DATE | An energy-aware fault tolerant scheduling framework for soft error resilient cloud computing systems. | Yue Gao, Sandeep K. Gupta, Yanzhi Wang, Massoud Pedram |
| 2014 | ITC | Optimizing redundancy design for chip-multiprocessors for flexible utility functions. | Da Cheng, Sandeep K. Gupta |
| 2013 | DATE | Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize cost. | Byeongju Cha, Sandeep K. Gupta |
| 2013 | DATE | Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors. | Yue Gao, Sandeep K. Gupta, Melvin A. Breuer |
| 2013 | ICCD | Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits. | Prasanjeet Das, Sandeep K. Gupta |
| 2013 | VTS | Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning. | Prasanjeet Das, Sandeep K. Gupta |
| 2012 | DATE | Salvaging chips with caches beyond repair. | Hsunwei Hsiung, Byeongju Cha, Sandeep K. Gupta |
| 2012 | ITC | A design flow to maximize yield/area of physical devices via redundancy. | Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta |
| 2011 | DATE | A new circuit simplification method for error tolerant applications. | Doochul Shin, Sandeep K. Gupta |
| 2010 | DATE | Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules. | Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta |
| 2010 | DATE | Approximate logic synthesis for error tolerant applications. | Doochul Shin, Sandeep K. Gupta |
| 2010 | ITC | Design and test of latch-based circuits to maximize performance, yield, and delay test quality. | Kun Young Chung, Sandeep K. Gupta |
| 2009 | ITC | Tolerance of performance degrading faults for effective yield improvement. | Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee |
| 2009 | VTS | Efficient Scheduling of Path Delay Tests for Latch-Based Circuits. | Kun Young Chung, Sandeep K. Gupta |
| 2008 | ICCD | Characterization of granularity and redundancy for SRAMs for optimal yield-per-area. | Jae Chul Cha, Sandeep K. Gupta |
| 2008 | ISPDC | Data Partitioning and Placement Schemes for Matrix Multiplications on a PIM Architecture. | Jae Chul Cha, Sandeep K. Gupta |
| 2008 | ITC | On Accelerating Path Delay Fault Simulation of Long Test Sequences. | I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta |
| 2008 | VTS | An Industrial Case Study of Sticky Path-Delay Faults. | I-De Huang, Yi-Shing Chang, Sandeep K. Gupta, Sreejit Chakravarty |
| 2007 | ICCD | Accurate modeling and fault simulation of Byzantine resistive bridges. | Hugo Cheung, Sandeep K. Gupta |
| 2007 | ITC | ERTG: A test generator for error-rate testing. | Shideh Shahidi, Sandeep K. Gupta |
| 2006 | DATE | STAX: statistical crosstalk target set compaction. | Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer |
| 2006 | ICCD | A theory of Error-Rate Testing. | Shideh Shahidi, Sandeep K. Gupta |
| 2006 | ITC | Estimating Error Rate during Self-Test via One's Counting. | Shideh Shahidi, Sandeep K. Gupta |
| 2006 | VTS | Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing. | Kun Young Chung, Sandeep K. Gupta |
| 2005 | ITC | Multiple tests for each gate delay fault: higher coverage and lower test application cost. | Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer |
| 2004 | ITC | Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. | Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer |
| 2004 | VTS | Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip. | Md. Saffat Quasem, Sandeep K. Gupta |
| 2003 | ITC | Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing. | Kun Young Chung, Sandeep K. Gupta |
| 2003 | VTS | Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets. | Nabil M. Abdulrazzaq, Sandeep K. Gupta |
| 2003 | VTS | Generating Complete and Optimal March Tests for Linked Faults in Memories. | Sultan M. Al-Harbi, Sandeep K. Gupta |
| 2003 | VTS | Test Generation for Maximizing Ground Bounce Considering Circuit Delay. | Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer |
| 2003 | VTS | Analyzing Crosstalk in the Presence of Weak Bridge Defects. | Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer |
| 2002 | ICCD | Accurate and Efficient Static Timing Analysis with Crosstalk. | I-De Huang, Sandeep K. Gupta, Melvin A. Breuer |
| 2002 | ITC | An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes. | Zhigang Jiang, Sandeep K. Gupta |
| 2002 | ITC | XIDEN: Crosstalk Target Identification Framework. | Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer |
| 2001 | DAC | A New Gate Delay Model for Simultaneous Switching and Its Applications. | Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer |
| 2001 | DATE | Exact fault simulation for systems on Silicon that protects each core's intellectual property. | Md. Saffat Quasem, Sandeep K. Gupta |
| 2001 | ITC | Crosstalk test generation on pseudo industrial circuits: a case study. | Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer |
| 2001 | ITC | Switch-level delay test of domino logic circuits. | Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer |
| 2001 | VTS | An Efficient Methodology for Generating Optimal and Uniform March Tests. | Sultan M. Al-Harbi, Sandeep K. Gupta |
| 2001 | VTS | Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. | Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer |
| 2000 | ITC | Test generation for path-delay faults in one-dimensional iterative logic arrays. | Nabil M. Abdulrazzaq, Sandeep K. Gupta |
| 2000 | VLSID | New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. | Melvin A. Breuer, Sandeep K. Gupta |
| 2000 | VTS | A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study. | Hugo Cheung, Sandeep K. Gupta |
| 1999 | ICCAD | Validation and test generation for oscillatory noise in VLSI interconnects. | Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer |
| 1999 | ITC | Test generation for crosstalk-induced delay in integrated circuits. | Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer |
| 1999 | ITC | Switch-level delay test. | Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer |
| 1999 | ITC | LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation. | Seongmoon Wang, Sandeep K. Gupta |
| 1999 | VTS | Test Generation for Ground Bounce in Internal Logic Circuitry. | Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer |
| 1998 | DAC | Introducing Redundant Computations in a Behavior for Reducing BIST Resources. | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer |
| 1998 | DATE | Scheduling and Module Assignment for Reducing Bist Resources. | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer |
| 1998 | ICCD | Efficient BIST TPG design and test set compaction for delay testing via input reduction. | Chih-Ang Chen, Sandeep K. Gupta |
| 1998 | ITC | Test generation in VLSI circuits for crosstalk noise. | Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer |
| 1998 | ITC | A new path-oriented effect-cause methodology to diagnose delay failures. | Yuan-Chieh Hsu, Sandeep K. Gupta |
| 1998 | VTS | A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags. | Sultan M. Al-Harbi, Sandeep K. Gupta |
| 1997 | DAC | ATPG for Heat Dissipation Minimization During Scan Testing. | Seongmoon Wang, Sandeep K. Gupta |
| 1997 | ICCAD | BIST TPG for faults in system backplanes. | Chen-Huan Chiang, Sandeep K. Gupta |
| 1997 | ITC | Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. | Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta |
| 1997 | ITC | DS-LFSR: A New BIST TPG for Low Heat Dissipation. | Seongmoon Wang, Sandeep K. Gupta |
| 1997 | VTS | Analysis of Ground Bounce in Deep Sub-Micron Circuits. | Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer |
| 1997 | VTS | High Quality Robust Tests for Path Delay Faults. | Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer |
| 1997 | VTS | BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. | Chen-Huan Chiang, Sandeep K. Gupta |
| 1996 | DAC | A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts. | Chih-Ang Chen, Sandeep K. Gupta |
| 1996 | DAC | Lower Bounds on Test Resources for Scheduled Data Flow Graphs. | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer |
| 1996 | ITC | Process-Aggravated Noise (PAN): New Validation and Test Problems. | Melvin A. Breuer, Sandeep K. Gupta |
| 1996 | ITC | A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation. | Hugo Cheung, Sandeep K. Gupta |
| 1996 | VTS | Delay Fault Testing: How Robust are Our Models? | Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma |
| 1995 | CPM | Making the Shortest-Paths Approach to Sum-of-Pairs Multiple Sequence Alignment More Space Efficient in Practice (Extended Abstract). | Sandeep K. Gupta, John D. Kececioglu, Alejandro A. Schffer |
| 1995 | DAC | Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer |
| 1995 | HotOS | AVM: application-level virtual memory. | Dawson R. Engler, Sandeep K. Gupta, M. Frans Kaashoek |
| 1995 | ITC | A Methodology to Design Efficient BIST Test Pattern Generators. | Chih-Ang Chen, Sandeep K. Gupta |
| 1994 | DAC | Clock Grouping: A Low Cost DFT Methodology for Delay Testing. | Wen-Chang Fang, Sandeep K. Gupta |
| 1994 | ICCAD | Random pattern testable logic synthesis. | Chen-Huan Chiang, Sandeep K. Gupta |
| 1994 | ITC | ATPG for Heat Dissipation Minimization During Test Application. | Seongmoon Wang, Sandeep K. Gupta |
| 1994 | VTS | Test embedding with discrete logarithms. | Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer |
| 1994 | VTS | Weighted random robust path delay testing of synthesized multilevel circuits. | Weili Wang, Sandeep K. Gupta |
| 1993 | DAC | An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. | Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer |
| 1993 | ITC | Novel Test Pattern Generators for Pseudo-Exhaustive Testing. | Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer |
| 1992 | ITC | Can Concurrent Checkers Help BIST? | Sandeep K. Gupta, Dhiraj K. Pradhan |
| 1992 | VTS | Recent advances in BIST. | Sandeep K. Gupta |
| 1991 | ITC | Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model. | Mark G. Karpovsky, Sandeep K. Gupta, Dhiraj K. Pradhan |
| 1988 | ITC | Concurrent Control of Multiple BIT Structures. | Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien |
| 1988 | ITC | A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability. | Sandeep K. Gupta, Dhiraj K. Pradhan |