| 2015 | ICCAD | Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading. | Ankur Sharma, David G. Chinnery, Sarvesh Bhardwaj, Chris C. N. Chu |
| 2014 | DAC | On Timing Closure: Buffer Insertion for Hold-Violation Removal. | Pei-Ci Wu, Martin D. F. Wong, Ivailo Nedelchev, Sarvesh Bhardwaj, Vidyamani Parkhe |
| 2008 | VLSID | Power Reduction of Functional Units Considering Temperature and Process Variations. | Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
| 2008 | VLSID | Temperature and Process Variations Aware Power Gating of Functional Units. | Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
| 2007 | DAC | The Impact of NBTI on the Performance of Combinational and Sequential Circuits. | Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao |
| 2007 | VLSID | A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. | Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
| 2007 | VLSID | Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. | Sarma B. K. Vrudhula, Sarvesh Bhardwaj |
| 2006 | ASPDAC | Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. | Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula |
| 2006 | DAC | Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao |
| 2006 | DAC | Stochastic variational analysis of large power grids considering intra-die correlations. | Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda |
| 2006 | ICCAD | A framework for statistical timing analysis using non-linear delay and slew models. | Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula |
| 2005 | ASPDAC | An efficient combinationality check technique for the synthesis of cyclic combinational circuits. | Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang |
| 2005 | DAC | Leakage minimization of nano-scale circuits in the presence of systematic and random variations. | Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
| 2005 | ICCAD | Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. | Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
| 2004 | VLSID | Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. | Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj |
| 2003 | ICCAD | AU: Timing Analysis Under Uncertainty. | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw |
| 2002 | ICCAD | Estimation of signal arrival times in the presence of delay noise. | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw |