Shianling Wu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
4
Active years
1985–2010
Best venue rank
A
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | VTS | CSER: BISER-based concurrent soft-error resilience. | Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li |
| 2008 | ITC | Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. | Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li |
| 2006 | ITC | A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing. | Hiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu |
| 2005 | DATE | At-Speed Logic BIST for IP Cores. | B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu |
| 2005 | ICCD | At-Speed Logic BIST Architecture for Multi-Clock Designs. | Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo |
| 2005 | ITC | UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction. | Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang |
| 2005 | ITC | Test compression and logic BIST at your fingertips. | Shianling Wu, Laung-Terng Wang, Jin Woo Cho, Zhigang Jiang, Boryau Sheu |
| 2004 | ITC | VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. | Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai |
| 1998 | ITC | A non-enumerative path delay fault simulator for sequential circuits. | Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu |
| 1985 | ITC | A Sequential Circuit Test Generation System. | Sivanarayana Mallela, Shianling Wu |