| 2025 | ISCAS | PAT-ViT: Token Pruning-based Adversarial Tuning for Robust Vision Transformers. | Yun-Hao Yang, Yuan-June Luo, Wan-Jung Chen, An-Yeu Andy Wu, Shih-Hsu Huang, Mladen Berekovic |
| 2024 | ISCAS | Design Flow for Incorporating Camouflaged Logic Gates to Enhance Hardware Security While Considering Timing Closure. | Liang-Ying Su, Shih-Hsu Huang |
| 2020 | VTS | Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. | Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng |
| 2018 | MICRO | Keynote Talk: 3D Core-based SoC Testing for Low Power and TSV Count Minimization. | Shih-Hsu Huang |
| 2017 | ICCAD | Overview of the 2017 CAD contest at ICCAD: Invited paper. | Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake |
| 2016 | ICCAD | Overview of the 2016 CAD contest at ICCAD. | Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake |
| 2016 | ISCAS | Top-level activity-driven clock tree synthesis with clock skew variation considered. | Te-Jui Wang, Shih-Hsu Huang, Wei-Kai Cheng, Yih-Chih Chou |
| 2015 | ICCAD | Overview of the 2015 CAD Contest at ICCAD. | Natarajan Viswanathan, Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim |
| 2014 | DATE | Leakage-power-aware clock period minimization. | Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh |
| 2013 | DATE | Co-synthesis of data paths and clock control paths for minimum-period clock gating. | Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng |
| 2013 | ICCAD | Low-power timing closure methodology for ultra-low voltage designs. | Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou |
| 2012 | ASPDAC | Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. | Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng |
| 2012 | ISCAS | NBTI-aware dual threshold voltage assignment for leakage power reduction. | Wen-Pin Tu, Shih-Wei Wu, Shih-Hsu Huang, Mely Chen Chi |
| 2012 | ISCAS | A formal approach to slack-driven high-level synthesis. | Hua-Hsin Yeh, Shih-Hsu Huang, Chun-Hua Cheng |
| 2010 | ASPDAC | Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. | Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan |
| 2009 | ASPDAC | Timing driven power gating in high-level synthesis. | Shih-Hsu Huang, Chun-Hua Cheng |
| 2009 | ISCAS | Surge Current Minimization in High-level Synthesis. | Jheng-Fu Yeh, Chun-Hua Cheng, Shih-Hsu Huang |
| 2008 | DAC | Type-matching clock tree for zero skew clock gating. | Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu |
| 2007 | DAC | Clock Period Minimization with Minimum Delay Insertion. | Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh |
| 2007 | EUC | A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs. | Shih-Hsu Huang, Chu-Liao Wang, Man-Lin Huang |
| 2007 | EUC | Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. | Wei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng |
| 2006 | ASPDAC | Fast multi-domain clock skew scheduling for peak current reduction. | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh |
| 2006 | DAC | Register binding for clock period minimization. | Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu |
| 2006 | ICCAD | State re-encoding for peak current minimization. | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh |
| 2005 | DAC | Race-condition-aware clock skew scheduling. | Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu |
| 2005 | DAC | Minimizing peak current via opposite-phase clock tree. | Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu |
| 2005 | ISCAS | A formal approach to the slack driven scheduling problem in high-level synthesis. | Shih-Hsu Huang, Chun-Hua Cheng |
| 2005 | ISCAS | VLSI implementation of type-2 fuzzy inference processor. | Shih-Hsu Huang, Yi-Rung Chen |
| 2005 | ISCAS | Floorplanning with clock tree estimation. | Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh |
| 2003 | ICCAD | Clock Period Minimization of Non-Zero Clock Skew Circuits. | Shih-Hsu Huang, Yow-Tyng Nieh |
| 2002 | ISCAS | An effective floorplan-based power distribution network design methodology under reliability constraints. | Shih-Hsu Huang, Chu-Liao Wang |
| 1995 | ASPDAC | Synthesis of false loop free circuits. | Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang |
| 1992 | MICRO | A new approach to schedule operations across nested-ifs and nested-loops. | Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang |