| 2025 | CIDR | Towards Foundation Database Models. | Johannes Wehrstein, Carsten Binnig, Fatma zcan, Shobha Vasudevan, Yu Gan, Yawen Wang |
| 2019 | ASPDAC | A figure of merit for assertions in verification. | Samuel Hertz, Debjit Pal, Spencer Offenberger, Shobha Vasudevan |
| 2019 | DATE | Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft Errors. | Keven Feng, Sandeep Vora, Rui Jiang, Elyse Rosenbaum, Shobha Vasudevan |
| 2018 | DAC | Application level hardware tracing for scaling post-silicon debug. | Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M. de Paula, Shobha Vasudevan |
| 2016 | ASPDAC | Every test makes a difference: Compressing analog tests to decrease production costs. | Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan |
| 2016 | ICCAD | Duplex: simultaneous parameter-performance exploration for optimizing analog circuits. | Seyed Nematollah Ahmadyan, Shobha Vasudevan |
| 2016 | VLSID | Symptomatic Bug Localization for Functional Debug of Hardware Designs. | Debjit Pal, Shobha Vasudevan |
| 2015 | DATE | Fast eye diagram analysis for high-speed CMOS circuits. | Seyed Nematollah Ahmadyan, Chenjie Gu, Suriyaprakash Natarajan, Eli Chiprout, Shobha Vasudevan |
| 2015 | ICCAD | Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection. | Sai Ma, Debjit Pal, Rui Jiang, Sandip Ray, Shobha Vasudevan |
| 2014 | DAC | Code Coverage of Assertions Using RTL Source Code Analysis. | Viraj Athavale, Sai Ma, Samuel Hertz, Shobha Vasudevan |
| 2014 | VLSID | A Coverage Guided Mining Approach for Automatic Generation of Succinct Assertions. | David Sheridan, Lingyi Liu, Hyungsul Kim, Shobha Vasudevan |
| 2013 | DATE | Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm. | Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan |
| 2013 | DATE | Reachability analysis of nonlinear analog circuits through iterative reachable set reduction. | Seyed Nematollah Ahmadyan, Shobha Vasudevan |
| 2013 | ICCAD | Diagnosing root causes of system level performance violations. | Lingyi Liu, Xuanyu Zhong, Xiaotao Chen, Shobha Vasudevan |
| 2012 | ASPDAC | Verifying dynamic power management schemes using statistical model checking. | Jayanand Asok Kumar, Shobha Vasudevan |
| 2012 | DAC | Goal-oriented stimulus generation for analog circuits. | Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan |
| 2012 | DAC | Early prediction of NBTI effects using RTL source code analysis. | Jayanand Asok Kumar, Kenneth M. Butler, Heesoo Kim, Shobha Vasudevan |
| 2012 | ICCAD | Word level feature discovery to enhance quality of assertion mining. | Lingyi Liu, Chen-Hsuan Lin, Shobha Vasudevan |
| 2011 | DATE | Towards coverage closure: Using GoldMine assertions for generating design validation stimulus. | Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan |
| 2011 | DATE | Efficient validation input generation in RTL by hybridized source code analysis. | Lingyi Liu, Shobha Vasudevan |
| 2011 | FMCAD | Scaling probabilistic timing verification of hardware using abstractions in design source code. | Jayanand Asok Kumar, Lingyi Liu, Shobha Vasudevan |
| 2011 | ICDM | Signature Pattern Covering via Local Greedy Algorithm and Pattern Shrink. | Hyungsul Kim, Sungjin Im, Tarek F. Abdelzaher, Jiawei Han, David Sheridan, Shobha Vasudevan |
| 2011 | MEMOCODE | Automatic generation of assertions from system level design using data mining. | Lingyi Liu, David Sheridan, Viraj Athavale, Shobha Vasudevan |
| 2011 | VLSID | Variation-Conscious Formal Timing Verification in RTL. | Jayanand Asok Kumar, Shobha Vasudevan |
| 2011 | VTS | Coverage closure in SoC verification: Are we chasing a mirage? | Shobha Vasudevan |
| 2010 | DATE | GoldMine: Automatic assertion generation using data mining and static analysis. | Shobha Vasudevan, David Sheridan, Sanjay J. Patel, David Tcheng, William Tuohy, Daniel R. Johnson |
| 2010 | DSN | Statistical guarantees of performance for MIMO designs. | Jayanand Asok Kumar, Shobha Vasudevan |
| 2009 | VLSID | Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. | Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham |
| 2007 | VLSID | Efficient Microprocessor Verification using Antecedent Conditioned Slicing. | Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham |
| 2006 | ITC | Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor. | Sankar Gurumurthy, Shobha Vasudevan, Jacob A. Abraham |
| 2006 | MEMOCODE | Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. | Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu |
| 2005 | ITC | Automated mapping of pre-computed module-level test sequences to processor instructions. | S. Guramurthy, Shobha Vasudevan, Jacob A. Abraham |