| 2026 | ISCAS | Neural Network-Based Contiguous Carrier Aggregation Digital Predistortion Design for Sub-THz Power Amplifier in Baseband Transmitter. | Cheng-Hsuan Lai, Chung-Lun Tu, Yi-Shan Huang, Shyh-Jye Jou |
| 2026 | ISCAS | A 66.15 TFLOPS/W RRAM-based Near-memory-computing Macro using Log-multiplication and Error-aware Adaptive Adder Structure with 2-D Pipelined CNN Dataflow. | Yue-Ci Lee, Yuan-Ping Huang, Shyh-Jye Jou |
| 2026 | ISCAS | High Throughput LDPC Decoder with Ultra-low BER Using Hardware Sharing across Two Code Rates for IEEE Std. 802.15.3d. | Ching Liang Yeh, Yi-Shan Huang, Chung-Lun Tu, Shyh-Jye Jou |
| 2025 | ISCAS | A Deep Learning Accelerator for Modified YOLOv7-tiny with Shortcut-Aware Layer Fusion. | Wei-En Huang, Yi-Shan Huang, Shyh-Jye Jou |
| 2024 | DATE | A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application. | Kuan-Chih Lin, Hao Zuo, Hsiang-Yu Wang, Yuan-Ping Huang, Ci-Hao Wu, Yan-Cheng Guo, Shyh-Jye Jou, Tuo-Hung Hou, Tian-Sheuan Chang |
| 2024 | ISCAS | Online Self-Adaptive Estimation and Compensation Design for DC Voltage Offset, Frequency-Independent, and Frequency-Dependent IQ Mismatch in Sub-THz Digital Baseband Transceiver. | Chia-Jung Lee, Chung-Lun Tu, Shyh-Jye Jou |
| 2024 | ISCAS | Channel Estimation and Equalization Design with SNR Decision Based Universal Threshold for Sub-THz Single Carrier Baseband Receiver. | Feng-Ju Liao, Chung-Lun Tu, Shyh-Jye Jou |
| 2024 | ISCAS | A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks. | Tsung-Han Wu, Ching Liang Yeh, Yi-Shan Huang, Shyh-Jye Jou |
| 2023 | ASPDAC | On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. | Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen |
| 2023 | ISCAS | Offline and Time-variant EVD-based Closed-loop Digital Predistortion Design for Sub-THz Power Amplifier Array in Basedband Transmitter. | Chung-Lun Tu, Chin-Ming Chang, Shyh-Jye Jou |
| 2022 | DATE | DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks. | Bo-Cheng Lai, Tzu-Chieh Chiang, Po-Shen Kuo, Wan-Ching Wang, Yan-Lin Hung, Hung-Ming Chen, Chien-Nan Liu, Shyh-Jye Jou |
| 2022 | ISCAS | Design of a mmWave Digital Baseband Receiver Integrated with WOLA-CP-OFDM Technique. | Kang-Lun Chiu, Hsun-Wei Chan, Hsuan-Ping Chiu, Chun-Yi Liu, Chih-Wei Jen, Shyh-Jye Jou |
| 2022 | ISCAS | Low-Complexity Pseudo Direct Learning Digital Pre-Distortion Architecture for Nonlinearity and Memory Effect of Power Amplifier in mmWave Baseband Transmitter. | Shen-Zhe Lu, Nai-Cheng Xue, Hung-Chih Liu, Chih-Wei Jen, Shyh-Jye Jou |
| 2022 | ISCAS | Compressive Sensing Based Hardware Design for Channel Estimation of Wideband Millimeter Wave Hybrid MIMO System. | Chung-Lun Tu, Tse-Yuan Lin, Kang-Lun Chiu, Shyh-Jye Jou, Pei-Yun Tsai |
| 2021 | ISCAS | A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO. | Chia-Chen Chang, Yu-Tung Chin, Hossameldin A. Ibrahim, Kang-Yu Chang, Shyh-Jye Jou |
| 2020 | ICCAD | On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. | Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Kster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou |
| 2020 | ISCAS | Digital Self-Healing using Smart Sensing Technique for IQ Mismatch and LO Leakage against Non-Flat Path Response in mmWave Communication System. | Ngoc-Giang Doan, Hung-Chih Liu, Chih-Wei Jen, Shyh-Jye Jou |
| 2019 | ISCAS | A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems. | Chee-Kit Ng, Kang-Lun Chiu, Yu-Chun Lin, Shyh-Jye Jou |
| 2018 | ISCAS | Digital Self-Interference Cancellation for OFDM Full-Duplex Transmission in 60 GHz Band. | Chih-Wei Jen, Hung-Wei Yang, Hsun-Wei Chan, Hung-Chih Liu, Henry Lopez Davila, Chun-Yi Liu, Shyh-Jye Jou |
| 2018 | ISCAS | A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems. | Chee-Kit Ng, Yu-Chun Lin, Wei-Chang Liu, Chih-Feng Wu, Shyh-Jye Jou |
| 2017 | ISCAS | Residual sampling clocking offset estimation and compensation for FBMC-OQAM baseband receiver in the 60 GHz band. | Chun-Yi Liu, Yu-Cheng Yao, Meng-Siou Sie, Edmund Wen Jen Leong, Henry Lopez Davila, Chih-Wei Jen, Shyh-Jye Jou |
| 2016 | ICASSP | Error-resilient sequential cells with successive time borrowing for stochastic computing. | Wei-Chang Liu, Ching-Da Chan, Shuo-An Huang, Chi-Wei Lo, Chia-Hsiang Yang, Shyh-Jye Jou |
| 2016 | ISCAS | A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. | Yi-Wei Chiu, Yu-Hao Hu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang |
| 2016 | ISCAS | A memory access reordering polyphase network for 60 GHz FBMC-OQAM baseband receiver. | Chun-Yi Liu, Meng-Siou Sie, Edmund Wen Jen Leong, Yu-Cheng Yao, Chih-Wei Jen, Shyh-Jye Jou |
| 2015 | ISCAS | A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive. | Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee |
| 2014 | ICASSP | An efficient 18-band quasi-ANSI 1/3-octave filter bank using re-sampling method for digital hearing aids. | Cheng-Yen Yang, Chih-Wei Liu, Shyh-Jye Jou |
| 2014 | ISCAS | An ultra-low voltage hearing aid chip using variable-latency design technique. | Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Chih-Wei Liu, Yuan-Hua Chu, Shyh-Jye Jou |
| 2014 | ISCAS | An IEEE 802.15.3c/802.11ad compliant SC/OFDM dual-mode baseband receiver for 60 GHz Band. | Wei-Chang Liu, Fu-Chun Yeh, Chia-Yi Wu, Ting-Chen Wei, Ya-Shiue Huang, Shen-Jui Huang, Ching-Da Chan, Shyh-Jye Jou, Sau-Gee Chen |
| 2013 | ISCAS | A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. | Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih |
| 2013 | ISCAS | A SC/HSI dual-mode baseband receiver with frequency-domain equalizer for IEEE 802.15.3c. | Wei-Chang Liu, Fu-Chun Yeh, Ting-Chen Wei, Ya-Shiue Huang, Tai-Yang Liu, Shen-Jui Huang, Ching-Da Chan, Shyh-Jye Jou, Sau-Gee Chen |
| 2013 | ISLPED | A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. | Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang |
| 2012 | ISCAS | An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. | Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu |
| 2012 | ISCAS | High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. | Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu |
| 2012 | ITC | Testing strategies for a 9T sub-threshold SRAM. | Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango Chia-Tso Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang |
| 2011 | ISCAS | Low power InfomaxICA with compensation strategy for binaural hearing-aid. | Fan-Chiang Yi, Ching-Wen Huang, Tai-Shih Chi, Shyh-Jye Jou |
| 2011 | ISLPED | 8T single-ended sub-threshold SRAM with cross-point data-aware write operation. | Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang |
| 2009 | ISCAS | 10Gbps Decision Feedback Equalizer with Dynamic Lookahead Decision Loop. | Yu-Chun Lin, Muh-Tian Shiue, Shyh-Jye Jou |
| 2008 | ISCAS | Symbol and carrier frequency offset synchronization for IEEE802.16e. | Jyun-Nan Lin, Hsiao-Yun Chen, Ting-Chen Wei, Shyh-Jye Jou |
| 2008 | ISCAS | A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. | Li-Rong Wang, Yi-Wei Chiu, Chia-Lin Hu, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee |
| 2007 | ICASSP | Novel Programmable FIR Filter Based on Higher Radix Recoding for Low-Power and High-Performance Applications. | Hsiao-Yun Chen, Shyh-Jye Jou |
| 2007 | ISCAS | Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/H. | Wei-Chang Liu, Ting-Chen Wei, Shyh-Jye Jou |
| 2006 | ISCAS | Memory reduction ICFO estimation architecture for DVB-T. | Ting-Zhen Wei, Shyh-Jye Jou, Muh-Tian Shiue |
| 2005 | ISCAS | A 12.5 Gbps CMOS input sampler for serial link receiver front end. | Shyh-Jye Jou, Chih-Hsien Lin, Yen-I Wang |
| 2004 | ISCAS | A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. | Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu |
| 2004 | ISCAS | 4/2 PAM serial link transmitter with tunable pre-emphasis. | Chih-Hsien Lin, Chang-Hsiao Tsai, Chih-Ning Chen, Shyh-Jye Jou |
| 2003 | ASPDAC | 5Gbps serial link transmitter with pre-emphasis. | Chih-Hsien Lin, Chung-Hong Wang, Shyh-Jye Jou |
| 2003 | ASPDAC | Low-power digital CDMA receiver. | Ja-Sheng Liu, I-Hsin Chen, Yi-Chen Tsai, Shyh-Jye Jou |
| 2003 | ISCAS | Parameterized and low power DSP core for embedded systems. | Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-Jye Jou |
| 2002 | ISCAS | An embedded DSP core for wireless communication. | Shyh-Jye Jou, Hsiao Ping Lee, Yi-Ting Chen, Ming Hsuan Tan, Ya-Lan Tsao |
| 2002 | ISCAS | Sub-word and reduced-width Booth multipliers for DSP applications. | Meng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou |
| 2001 | ISCAS | A serial link transceiver for USB2 high-speed mode. | Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Chu King, Chien-Hsiung Lee, Tim Liu |
| 2001 | ISCAS | Low-power multiplierless FIR filter synthesizer based on CSD code. | Maw-Ching Lin, Chien-Lung Chen, Ding-Yu Shin, Chin-Hung Lin, Shyh-Jye Jou |
| 2000 | ICCD | Fixed-Width Multiplier for DSP Application. | Shyh-Jye Jou, Hui-Hsuan Wang |
| 1997 | ASPDAC | Structural approach for performance driven ECC circuit synthesis. | Chauchin Su, Kathy Y. Chen, Shyh-Jye Jou |
| 1997 | ITC | Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. | Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou |
| 1996 | DATE | Decentralized BIST for 1149.1 and 1149.5 Based Interconnects. | Chauchin Su, Shyh-Jye Jou, Yuan-Tzu Ting |
| 1996 | ICCAD | Metrology for analog module testing using analog testability bus. | Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting |
| 1995 | ICCAD | Impulse response fault model and fault extraction for functional level analog circuit diagnosis. | Chauchin Su, Shenshung Chiang, Shyh-Jye Jou |
| 1995 | ISCAS | A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors. | Wen-Hsing Hsieh, Shyh-Jye Jou, Chauchin Su |
| 1995 | ISCAS | Circuits Design Optimization Using Symbolic Approach. | Shyh-Jye Jou, Kou-Fong Liu, Chauchin Su |
| 1994 | ISCAS | Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits. | Shyh-Jye Jou, Mei-Fang Perng, Chauchin Su, C. K. Wang |
| 1994 | ITC | An I | Chauchin Su, Kychin Hwang, Shyh-Jye Jou |