Simon W. Moore
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
49
Venues
22
Active years
1998–2026
Best venue rank
A*
Where they publish
- CICCD10 papers
- BFPL6 papers
- A*ASPLOS5 papers
- CDSD3 papers
- A*MICRO3 papers
- A*SP3 papers
- ACHES3 papers
- A*ISCA2 papers
- A*SOSP1 paper
- CPDP1 paper
- A*CCS1 paper
- A*NDSS1 paper
- BFMCAD1 paper
- CMEMOCODE1 paper
- NationalFCCM1 paper
- AFPGA1 paper
- BSPAA1 paper
- BASPDAC1 paper
- CCARDIS1 paper
- CISCAS1 paper
- NationalVLSID1 paper
- NationalSGAI1 paper
Papers
49 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ASPLOS | CHERI-SIMT: Implementing Capability Memory Protection in GPUs. | Matthew Naylor, Alexandre Joannou, A. Theodore Markettos, Paul Metzger, Simon W. Moore, Timothy M. Jones |
| 2025 | SOSP | CHERIoT RTOS: An OS for Fine-Grained Memory-Safe Compartments on Low-Cost Embedded Devices. | Saar Amar, Tony Chen, David Chisnall, Nathaniel Wesley Filardo, Ben Laurie, Hugo Lefeuvre, Kunyan Liu, Simon W. Moore, Robert Norton-Wright, Margo I. Seltzer, Yucong Tao, Robert N. M. Watson, Hongyan Xia |
| 2024 | ASPLOS | Cornucopia Reloaded: Load Barriers for CHERI Heap Temporal Safety. | Nathaniel Wesley Filardo, Brett F. Gutstein, Jonathan Woodruff, Jessica Clarke, Peter Rugg, Brooks Davis, Mark Johnston, Robert M. Norton, David Chisnall, Simon W. Moore, Peter G. Neumann, Robert N. M. Watson |
| 2024 | DSD | A Suite of Processors to Explore CHERI-RISC-V Micro Architecture. | Peter Rugg, Jonathan Woodruff, Alexandre Joannou, Simon W. Moore |
| 2024 | ICCD | Safe Speculation for Cheri. | Franz A. Fuchs, Jonathan Woodruff, Peter Rugg, Alexandre Joannou, Jessica Clarke, John Baldwin, Brooks Davis, Peter G. Neumann, Robert N. M. Watson, Simon W. Moore |
| 2024 | ICCD | Advanced Dynamic Scalarisation for RISC-V GPGPUs. | Matthew Naylor, Alexandre Joannou, A. Theodore Markettos, Paul Metzger, Simon W. Moore, Timothy M. Jones |
| 2023 | ICCD | Architectural Contracts for Safe Speculation. | Franz A. Fuchs, Jonathan Woodruff, Peter Rugg, Marno van der Maas, Alexandre Joannou, Alexander Richardson, Jessica Clarke, Nathaniel Wesley Filardo, Brooks Davis, John Baldwin, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson |
| 2023 | MICRO | CHERIoT: Complete Memory Safety for Embedded Devices. | Saar Amar, David Chisnall, Tony Chen, Nathaniel Wesley Filardo, Ben Laurie, Kunyan Liu, Robert M. Norton, Simon W. Moore, Yucong Tao, Robert N. M. Watson, Hongyan Xia |
| 2021 | PDP | General hardware multicasting for fine-grained message-passing architectures. | Matthew Naylor, Simon W. Moore, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown |
| 2020 | CCS | Protecting Enclaves from Intra-Core Side-Channel Attacks through Physical Isolation. | Marno van der Maas, Simon W. Moore |
| 2020 | MICRO | Position Paper: Defending Direct Memory Access with CHERI Capabilities. | A. Theodore Markettos, John Baldwin, Ruslan Bukin, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson |
| 2020 | SP | Cornucopia: Temporal Safety for CHERI Heaps. | Nathaniel Wesley Filardo, Brett F. Gutstein, Jonathan Woodruff, Sam Ainsworth, Lucian Paul-Trifu, Brooks Davis, Hongyan Xia, Edward Tomasz Napierala, Alexander Richardson, John Baldwin, David Chisnall, Jessica Clarke, Khilan Gudka, Alexandre Joannou, A. Theodore Markettos, Alfredo Mazzinghi, Robert M. Norton, Michael Roe, Peter Sewell, Stacey D. Son, Timothy M. Jones, Simon W. Moore, Peter G. Neumann, Robert N. M. Watson |
| 2020 | SP | Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process. | Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiss, Anthony C. J. Fox, Michael Roe, Brian Campbell, Matthew Naylor, Robert M. Norton, Simon W. Moore, Peter G. Neumann, Ian Stark, Robert N. M. Watson, Peter Sewell |
| 2019 | ASPLOS | CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment. | Brooks Davis, Robert N. M. Watson, Alexander Richardson, Peter G. Neumann, Simon W. Moore, John Baldwin, David Chisnall, Jessica Clarke, Nathaniel Wesley Filardo, Khilan Gudka, Alexandre Joannou, Ben Laurie, A. Theodore Markettos, J. Edward Maste, Alfredo Mazzinghi, Edward Tomasz Napierala, Robert M. Norton, Michael Roe, Peter Sewell, Stacey D. Son, Jonathan Woodruff |
| 2019 | FPL | Tinsel: A Manythread Overlay for FPGA Clusters. | Matthew Naylor, Simon W. Moore, David B. Thomas |
| 2019 | MICRO | CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety. | Hongyan Xia, Jonathan Woodruff, Sam Ainsworth, Nathaniel Wesley Filardo, Michael Roe, Alexander Richardson, Peter Rugg, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson, Timothy M. Jones |
| 2019 | NDSS | Thunderclap: Exploring Vulnerabilities in Operating System IOMMU Protection via DMA from Untrustworthy Peripherals. | A. Theodore Markettos, Colin Rothwell, Brett F. Gutstein, Allison Pearce, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson |
| 2018 | ICCD | CheriRTOS: A Capability Model for Embedded Devices. | Hongyan Xia, Jonathan Woodruff, Hadrien Barral, Lawrence Esswood, Alexandre Joannou, Robert Kovacsics, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alexander Richardson, Simon W. Moore, Robert N. M. Watson |
| 2017 | ASPLOS | CHERI JNI: Sinking the Java Security Model into the C. | David Chisnall, Brooks Davis, Khilan Gudka, David Brazdil, Alexandre Joannou, Jonathan Woodruff, A. Theodore Markettos, J. Edward Maste, Robert M. Norton, Stacey D. Son, Michael Roe, Simon W. Moore, Peter G. Neumann, Ben Laurie, Robert N. M. Watson |
| 2017 | ICCD | Efficient Tagged Memory. | Alexandre Joannou, Jonathan Woodruff, Robert Kovacsics, Simon W. Moore, Alex Bradbury, Hongyan Xia, Robert N. M. Watson, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alfredo Mazzinghi, Alex Richardson, Stacey D. Son, A. Theodore Markettos |
| 2016 | FMCAD | A consistency checker for memory subsystem traces. | Matthew Naylor, Simon W. Moore, Alan Mujumdar |
| 2015 | ASPLOS | Beyond the PDP-11: Architectural Support for a Memory-Safe C Abstract Machine. | David Chisnall, Colin Rothwell, Robert N. M. Watson, Jonathan Woodruff, Munraj Vadera, Simon W. Moore, Michael Roe, Brooks Davis, Peter G. Neumann |
| 2015 | MEMOCODE | A generic synthesisable test bench. | Matthew Naylor, Simon W. Moore |
| 2015 | SP | CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization. | Robert N. M. Watson, Jonathan Woodruff, Peter G. Neumann, Simon W. Moore, Jonathan Anderson, David Chisnall, Nirav H. Dave, Brooks Davis, Khilan Gudka, Ben Laurie, Steven J. Murdoch, Robert M. Norton, Michael Roe, Stacey D. Son, Munraj Vadera |
| 2014 | FPL | Interconnect for commodity FPGA clusters: Standardized or customized? | A. Theodore Markettos, Paul James Fox, Simon W. Moore, Andrew W. Moore |
| 2014 | FPL | Rapid codesign of a soft vector processor and its compiler. | Matthew Naylor, Simon W. Moore |
| 2014 | ISCA | The CHERI capability model: Revisiting RISC in an age of risk. | Jonathan Woodruff, Robert N. M. Watson, David Chisnall, Simon W. Moore, Jonathan Anderson, Brooks Davis, Ben Laurie, Peter G. Neumann, Robert M. Norton, Michael Roe |
| 2013 | FPL | A spiking neural network on a portable FPGA tablet. | Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore |
| 2013 | FPL | Managing the FPGA memory wall: Custom computing or vector processing? | Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore |
| 2013 | FPL | A 64-bit MIPS processor running freebsd on a portable FPGA tablet. | Jonathan Woodruff, A. Theodore Markettos, Simon W. Moore |
| 2012 | FCCM | Bluehive - A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation. | Simon W. Moore, Paul James Fox, Steven J. T. Marsh, A. Theodore Markettos, Alan Mujumdar |
| 2012 | ICCD | Mamba: A scalable communication centric multi-threaded processor architecture. | Gregory A. Chadwick, Simon W. Moore |
| 2009 | CHES | The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators. | A. Theodore Markettos, Simon W. Moore |
| 2009 | FPGA | FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis. | Rosemary M. Francis, Simon W. Moore |
| 2008 | SPAA | Fractal communication in software data dependency graphs. | Daniel Greenfield, Simon W. Moore |
| 2006 | ASPDAC | The design and implementation of a low-latency on-chip network. | Robert Mullins, Andrew West, Simon W. Moore |
| 2006 | CARDIS | Implementing Cryptography on TFT Technology for Secure Display Applications. | Petros Oikonomakos, Jacques J. A. Fournier, Simon W. Moore |
| 2006 | DSD | Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography. | Jacques J. A. Fournier, Simon W. Moore |
| 2006 | DSD | An Asynchronous PLA with Improved Security Characteristics. | Petros Oikonomakos, Simon W. Moore |
| 2006 | ICCD | RasP: An Area-efficient, On-chip Network. | Simon Hollis, Simon W. Moore |
| 2006 | ISCAS | An area-efficient, pulse-based interconnect. | Simon Hollis, Simon W. Moore |
| 2006 | VLSID | An Asynchronous Interconnect Architecture for Device Security Enhancement. | Simon Hollis, Simon W. Moore |
| 2006 | SGAI | Adding question answering to an e-tutor for programming languages. | Kate Taylor, Simon W. Moore |
| 2005 | CHES | Security Evaluation Against Electromagnetic Analysis at Design Time. | Huiyun Li, A. Theodore Markettos, Simon W. Moore |
| 2004 | ISCA | Low-Latency Virtual-Channel Routers for On-Chip Networks. | Robert Mullins, Andrew West, Simon W. Moore |
| 2003 | CHES | Security Evaluation of Asynchronous Circuits. | Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert Mullins, George S. Taylor |
| 2002 | ICCD | JMA: The Java-Multithreading Architecture for Embedded Processors. | Panit Watcharawitch, Simon W. Moore |
| 2000 | ICCD | Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems. | Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson |
| 1998 | ICCD | Rapid prototyping of self-timed circuits. | Simon W. Moore, Peter Robinson |