| 2023 | ISCA | GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis. | Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das |
| 2021 | ISPASS | GenomicsBench: A Benchmark Suite for Genomics. | Arun Subramaniyan, Yufeng Gu, Timothy Dunn, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das |
| 2017 | ISCAS | Event-driven random backpropagation: Enabling neuromorphic deep learning machines. | Emre Neftci, Charles Augustine, Somnath Paul, Georgios Detorakis |
| 2016 | ISCAS | Synaptic sampling in hardware spiking neural networks. | Sadique Sheik, Somnath Paul, Charles Augustine, Chinnikrishna Kothapalli, Muhammad M. Khellah, Gert Cauwenberghs, Emre Neftci |
| 2014 | DATE | Energy-efficient hardware acceleration through computing in the memory. | Somnath Paul, Robert Karam, Swarup Bhunia, Ruchir Puri |
| 2012 | VLSID | Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks. | Anandaroop Ghosh, Somnath Paul, Swarup Bhunia |
| 2012 | VLSID | Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory. | Lei Wang, Somnath Paul, Swarup Bhunia |
| 2011 | FPGA | Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only). | Somnath Paul, Swarup Bhunia |
| 2010 | ISLPED | VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement. | Somnath Paul, Swarup Bhunia |
| 2009 | CHES | MERO: A Statistical Approach for Hardware Trojan Detection. | Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia |
| 2009 | ICCAD | A circuit-software co-design approach for improving EDP in reconfigurable frameworks. | Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia |
| 2009 | ICCAD | A variation-aware preferential design approach for memory based reconfigurable computing. | Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia |
| 2008 | ASPDAC | MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. | Somnath Paul, Swarup Bhunia |
| 2008 | DAC | Collective computing based on swarm intelligence. | Seetharam Narasimhan, Somnath Paul, Swarup Bhunia |
| 2008 | DAC | Reconfigurable computing using content addressable memory for improved performance and resource usage. | Somnath Paul, Swarup Bhunia |
| 2008 | DATE | Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. | Yu Zhou, Somnath Paul, Swarup Bhunia |
| 2008 | ICCAD | Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. | Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia |
| 2008 | VLSID | Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits. | Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia |
| 2007 | ICCAD | Low-overhead design technique for calibration of maximum frequency at multiple operating points. | Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia |
| 2007 | ICCD | Memory based computation using embedded cache for processor yield and reliability improvement. | Somnath Paul, Swarup Bhunia |
| 2007 | IOLTS | Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. | Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia |
| 2007 | VTS | VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. | Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia |
| 1998 | VLSID | Hardware/Software Co-design of a High-end Mixed Signal Microcontroller. | Pradeep K. Mishra, Somnath Paul, S. Venkataraman, Rajat Gupta |