| 2025 | ISCAS | Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware. | R. Kanda, Hugo Le Blevec, Naoya Onizawa, Mathieu Lonardon, Vincent Gripon, Takahiro Hanyu |
| 2025 | ISCAS | Design of a Low-Energy MTJ-Based Nonvolatile Register Based on a Differential Information Storing Scheme. | Tomoo Yoshida, Masanori Natsui, Takahiro Hanyu |
| 2024 | IJCNN | Design of a High-Speed and Low-Power Threshold Adjustment Unit for Battery-Free Edge Devices. | Fangcen Zhong, Masanori Natsui, Takahiro Hanyu |
| 2023 | ISCAS | High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control. | Fangcen Zhong, Masanori Natsui, Takahiro Hanyu |
| 2021 | ISCAS | High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians. | Naoya Onizawa, Takahiro Hanyu |
| 2019 | ACSSC | A Design Framework for Invertible Logic. | Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu |
| 2018 | FPGA | Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only). | Daisuke Suzuki, Takahiro Hanyu |
| 2018 | ISCAS | High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure. | Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata |
| 2017 | DATE | Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. | Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui |
| 2016 | FPL | A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure. | Daisuke Suzuki, Takahiro Hanyu |
| 2016 | ICASSP | Gammatone filter based on stochastic computation. | Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu |
| 2016 | ISCAS | Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. | Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu |
| 2015 | DATE | Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. | Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki |
| 2015 | IECON | Design of a computational nonvolatile RAM for a greedy energy-efficient VLSI processor. | Akira Mochizuki, Naoto Yube, Takahiro Hanyu |
| 2014 | ISCAS | A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. | Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi |
| 2014 | ISCAS | Energy-aware current-mode inter-chip link for a dependable GALS NoC platform. | Hirokatsu Shirahama, Akira Mochizuki, Yuma Watanabe, Takahiro Hanyu |
| 2013 | ISCAS | Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor. | Takahiro Hanyu |
| 2013 | ISCAS | MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. | Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi |
| 2012 | ASPDAC | Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. | Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu |
| 2012 | ISCAS | Variation-resilient current-mode logic circuit design using MTJ devices. | Youngkeun Kim, Masanori Natsui, Takahiro Hanyu |
| 2012 | ISCAS | High-speed simulator including accurate MTJ models for spintronics integrated circuit design. | Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh |
| 2012 | PRDC | Multi-chip NoCs for Automotive Applications. | Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu |
| 2011 | DATE | Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring. | Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu |
| 2011 | ISCAS | Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system. | Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu |
| 2010 | ISCAS | High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip. | Naoya Onizawa, Takahiro Hanyu |
| 2010 | VTS | Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impact. | Takahiro Hanyu |
| 2009 | DATE | MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. | Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu |
| 2009 | ISCAS | High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme. | Yo Ohtake, Naoya Onizawa, Takahiro Hanyu |
| 2007 | ASPDAC | Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic. | Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu |
| 2000 | PRDC | Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama |
| 1997 | ASPDAC | Low-power multiple-valued current-mode integrated circuit with current-source control and its application. | Takahiro Hanyu, Satoshi Kazama, Michitaka Kameyama |