Tetsushi Koide
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
39
Venues
9
Active years
1993–2020
Best venue rank
C
Where they publish
Papers
39 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | Tencon | Classification Method with CNN features and SVM for Computer-Aided Diagnosis System in Colorectal Magnified NBI Endoscopy. | Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shinji Tanaka |
| 2019 | ISCAS | A Hardware Implementation of Colorectal Tumor Classification for Endoscopic Video on Customizable DSP Toward Real-Time Computer-Aided Diagnosis System. | Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka, Takayuki Sugawara, Hiroshi Toishi, Masayuki Tsuji, Nobuo Tamba |
| 2018 | Tencon | Implementation of Computer-Aided Diagnosis System on Customizable DSP Core for Colorectal Endoscopic Images with CNN Features and SVM. | Takumi Okamoto, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Hiroshi Toishi, Takayuki Sugawara, Masayuki Tsuji, Masayuki Odagawa, Nobuo Tamba, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shinji Tanaka |
| 2018 | Tencon | An Image Analysis Method for Lettuce Leaf and Root Growth Analysis in Hydroponic Culture. | Takumi Okamoto, Yasunori Sakane, Tetsushi Koide, Atsushi Ogawa, Masashi Komine, Chiharu Sone, Yoshihiro Kaneta, Yukio Yaji, Kyoko Toyofuku, Takahiro Kamata, Ken Kimura, Yoko Ishikawa, Toshihiro Kasama, Wojciech-Piptr Bula, Yoshishige Endo, Ryo Miyake |
| 2016 | ACCV | Discriminative Subtree Selection for NBI Endoscopic Image Labeling. | Tsubasa Hirakawa, Toru Tamaki, Takio Kurita, Bisser Raytchev, Kazufumi Kaneda, Chaohui Wang, Laurent Najman, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka |
| 2014 | ISCAS | Pipeline scanning architecture with computation reduction for rectangle pattern matching in real-time traffic sign detection. | Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto, Mutsumi Omori |
| 2014 | ISCAS | FPGA implementation of feature extraction for colorectal endoscopic images with NBI magnification. | Tsubasa Mishima, Satoshi Shigemi, Anh-Tuan Hoang, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka |
| 2014 | ISCAS | Compact hardware oriented number recognition algorithm for real-time speed traffic-sign recognition. | Masaharu Yamamoto, Anh-Tuan Hoang, Mutsumi Omori, Tetsushi Koide |
| 2013 | FIE | Power electronics education using the integrated circuit consistent education system and TCAD. | Keisuke Konishi, Takeshi Tanaka, Tetsushi Koide |
| 2013 | ICIP | Smoothing posterior probabilities with a particle filter of dirichlet distribution for stabilizing colorectal NBI endoscopy recognition. | Tsubasa Hirakawa, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka |
| 2007 | ISCAS | Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. | Takeshi Kumaki, Tetsushi Koide, Hans Jrgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito |
| 2006 | ASPDAC | Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. | Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jrgen Mattausch |
| 2006 | CEC | A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA. | Ali Ahmadi, M. Arifin Ritonga, Md. Anwarul Abedin, Hans Jrgen Mattausch, Tetsushi Koide |
| 2006 | ISCAS | Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. | Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Kazutoshi Awane, Tetsushi Koide, Hans Jrgen Mattausch |
| 2005 | ASPDAC | A low-power video segmentation LSI with boundary-active-only architecture. | Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jrgen Mattausch |
| 2005 | AVSS | A parallel hardware design for parametric active contour models. | Ali Ahmadi, Md. Anwarul Abedin, Hans Jrgen Mattausch, Tetsushi Koide |
| 2005 | ISCAS | CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. | Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jrgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito |
| 2005 | ISCAS | Object tracking in video pictures based on image segmentation and pattern matching. | Takashi Morimoto, Osamu Kiriyama, Yohmei Harada, Hidekazu Adachi, Tetsushi Koide, Hans Jrgen Mattausch |
| 2005 | ISCAS | Design of superscalar processor with multi-bank register file. | Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jrgen Mattausch |
| 2004 | ASPDAC | 350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. | Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jrgen Mattausch |
| 2004 | ASPDAC | Compact 12-port multi-bank register file test-chip in 0.35m CMOS for highly parallel processors. | Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jrgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka |
| 2004 | ASPDAC | Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. | Yuji Yano, Tetsushi Koide, Hans Jrgen Mattausch |
| 2003 | ASPDAC | A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry. | Tetsushi Koide, Hans Jrgen Mattausch, Yuji Yano, Takayuki Gyohten, Yoshihiro Soda |
| 2000 | ASPDAC | Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. | Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi |
| 2000 | ASPDAC | Genetic algorithm accelerator GAA-II. | Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Masataka Yamane, Hajime Ueno |
| 2000 | ISCAS | An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair. | Shingo Nakaya, Tetsushi Koide, Shin'ichi Wakabayashi |
| 1999 | ASPDAC | Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. | Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide |
| 1999 | ASPDAC | An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. | Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta |
| 1998 | ASPDAC | A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. | Tetsushi Koide, Shin'ichi Wakabayashi |
| 1998 | PPSN | Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. | Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide |
| 1997 | ASPDAC | Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. | Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru |
| 1995 | ASPDAC | A new system partitioning method under performance and physical constraints for multi-chip modules. | Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida |
| 1995 | ASPDAC | A new performance driven placement method with the Elmore delay model for row based VLSIs. | Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru |
| 1995 | ASPDAC | A three-layer over-cell multi-channel routing method for a new cell model. | Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida |
| 1995 | ISCAS | An MCM Routing Algorithm Considering Crosstalk. | Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida |
| 1995 | ISCAS | A Verification Algorithm for Logic Circuits with Internal Variables. | Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida |
| 1994 | ISCAS | A Floorplanning Method with Topological Constraint Manipulation. | Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida |
| 1994 | ISCAS | A Systolic Graph Partitioning Algorithm for VLSI Design. | Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida |
| 1993 | ISCAS | Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. | Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida |