Thomas Wild
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
42
Venues
20
Active years
2002–2026
Best venue rank
A*
Where they publish
Papers
42 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | Multi-Partner Project: Advancing European Semiconductor and Chiplet Innovation Through the Bavarian Chip Design Center. | Hussam Amrouch, Jehaan Joseph, Michael Schirmer, Johannes Geier, Ulf Schlichtmann, Michael Meidinger, Thomas Wild, Andreas Herkersdorf, Jens Npel, Georg Sigl, Yicheng Zhang, Carsten Trinitis, Aswathy Nedumpalli Sankaranarayanan, Martin Schulz, Andreas Korb, Konrad Hohentanner |
| 2026 | ISCA | STEP: Spatial Footprint Prefetcher with Multi-Point Temporal Triggers. | Yuanji Ye, Oliver Lenke, Thomas Wild, Andreas Herkersdorf |
| 2025 | DATE | HiPerNoC: A High-Performance Network-an-Chip for Flexible and Scalable FPGA-Based SmartNICs. | Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf |
| 2024 | DATE | EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. | Patrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Jrgen Becker, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino Betancourt, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan, Albrecht Mayer |
| 2024 | DSD | ecoNIC: Saving Energy Through SmartNIC-Based Load Balancing of Mixed-Critical Ethernet Traffic. | Franz Biersack, Marco Liess, Markus Absmann, Fabiana Lotter, Thomas Wild, Andreas Herkersdorf |
| 2024 | DSD | FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar. | Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf |
| 2024 | GECCO | XCS with dynamic sized experience replay for memory constrained applications. | Anmol Surhonne, Manuel Wensauer, Florian Maurer, Thomas Wild, Andreas Herkersdorf |
| 2024 | PDP | FlexRoute: A Fast, Flexible and Priority-Aware Packet-Processing Design. | Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf |
| 2023 | DAC | HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification. | Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Clara Kowalsky, Thomas Wild, Andreas Herkersdorf |
| 2023 | GECCO | LCT-DER: Learning Classifier Table with Dynamic-Sized Experience Replay for Run-time SoC Performance-Power Optimization. | Anmol Surhonne, Florian Maurer, Thomas Wild, Andreas Herkersdorf |
| 2023 | PDP | Priority-aware Inter-Server Receive Side Scaling. | Franz Biersack, Kilian Holzinger, Henning Stubbe, Thomas Wild, Georg Carle, Andreas Herkersdorf |
| 2022 | NOMS | SmartNIC-based Load Management and Network Health Monitoring for Time Sensitive Applications. | Kilian Holzinger, Franz Biersack, Henning Stubbe, Angela Gonzalez Mario, Abdoul Kane, Francesc Fons, Haigang Zhang, Thomas Wild, Andreas Herkersdorf, Georg Carle |
| 2021 | CoNEXT | Precise real-time monitoring of time-critical flows. | Kilian Holzinger, Henning Stubbe, Franz Biersack, Angela Gonzalez Mario, Abdoul Kane, Francisco Fons Lluis, Haigang Zhang, Thomas Wild, Andreas Herkersdorf, Georg Carle |
| 2021 | DATE | Long Short-Term Memory Neural Network-based Power Forecasting of Multi-Core Processors. | Mark Sagi, Martin Rapp, Heba Khdr, Yizhe Zhang, Nael Fasfous, Nguyen Anh Vu Doan, Thomas Wild, Jrg Henkel, Andreas Herkersdorf |
| 2020 | PDP | Inter-Server RSS: Extending Receive Side Scaling for Inter-Server Workload Distribution. | Andreas Oeldemann, Franz Biersack, Thomas Wild, Andreas Herkersdorf |
| 2018 | DATE | Design methodologies for enabling self-awareness in autonomous systems. | Armin Sadighi, Bryan Donyanavard, Thawra Kadeed, Kasra Moazzemi, Tiago Mck, Ahmed Nassar, Amir M. Rahmani, Thomas Wild, Nikil D. Dutt, Rolf Ernst, Andreas Herkersdorf, Fadi J. Kurdahi |
| 2018 | FPL | FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet. | Andreas Oeldemann, Thomas Wild, Andreas Herkersdorf |
| 2017 | DATE | A non-intrusive, operating system independent spinlock profiler for embedded multicore systems. | Lin Li, Philipp Wagner, Albrecht Mayer, Thomas Wild, Andreas Herkersdorf |
| 2017 | DSD | Adaptive Reliability for Fault Tolerant Multicore Systems. | Ihsen Alouani, Thomas Wild, Andreas Herkersdorf, Smal Niar |
| 2017 | PDCAT | A Divide and Conquer State Grouping Method for Bitmap Based Transition Compression. | Subramanian Shiva Shankar, Pinxing Lin, Andreas Herkersdorf, Thomas Wild |
| 2016 | DSD | Resolving Performance Interference in SR-IOV Setups with PCIe Quality-of-Service Extensions. | Andre Oliver Richter, Christian Herber, Thomas Wild, Andreas Herkersdorf |
| 2016 | ITNAC | Hardware acceleration of signature matching through multi-layer transition bit masking. | Subramanian Shiva Shankar, Pinxing Lin, Andreas Herkersdorf, Thomas Wild |
| 2016 | SCOPES | A Rule-based Methodology for Hardware Configuration Validation in Embedded Systems. | Lin Li, Philipp Wagner, Ramesh Ramaswamy, Albrecht Mayer, Thomas Wild, Andreas Herkersdorf |
| 2015 | DATE | Real-time capable CAN to AVB ethernet gateway using frame aggregation and scheduling. | Christian Herber, Andre Oliver Richter, Thomas Wild, Andreas Herkersdorf |
| 2015 | ICCD | A hardware-based multi-objective thread mapper for tiled manycore architectures. | Ravi Kumar Pujari, Thomas Wild, Andreas Herkersdorf |
| 2014 | DATE | System integration - The bridge between More than Moore and More Moore. | Andy Heinig, Manfred Dietrich, Andreas Herkersdorf, Felix Miller, Thomas Wild, Kai Hahn, Armin Grnewald, Rainer Brck, Steffen Krohnert, Jochen Reisinger |
| 2014 | FDL | Dependable task and communication migration in tiled manycore system-on-chip. | Stefan Wallentowitz, Stefan Rosch, Thomas Wild, Andreas Herkersdorf, Volker Wenzel, Jrg Henkel |
| 2014 | HPCC | Deadline-Aware Interrupt Coalescing in Controller Area Network (CAN). | Christian Herber, Andre Oliver Richter, Thomas Wild, Andreas Herkersdorf |
| 2014 | RTAS | A network virtualization approach for performance isolation in controller area network (CAN). | Christian Herber, Andre Oliver Richter, Thomas Wild, Andreas Herkersdorf |
| 2013 | DSD | AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections. | Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jrgen Teich, Jrgen Becker, Andreas Herkersdorf |
| 2013 | GI | Potentials and Challenges for Multi-Core Processors in Robotic Applications. | Andreas Herkersdorf, Johny Paul, Ravi Kumar Pujari, Walter Stechele, Stefan Wallentowitz, Thomas Wild, Aurang Zaib |
| 2012 | ASPDAC | Invasive manycore architectures. | Jrg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hbner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe |
| 2012 | DSD | TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs. | Felix Miller, Thomas Wild, Andreas Herkersdorf |
| 2012 | FDL | An integrated simulation framework for invasive computing. | Michael Gerndt, Frank Hannig, Andreas Herkersdorf, Andreas Hollmann, Marcel Meyer, Sascha Roloff, Josef Weidendorfer, Thomas Wild, Aurang Zaib |
| 2012 | FPL | A framework for Open Tiled Manycore System-On-Chip. | Stefan Wallentowitz, Andreas Lankes, Aurang Zaib, Thomas Wild, Andreas Herkersdorf |
| 2009 | DSD | Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources. | Andreas Lankes, Thomas Wild, Andreas Herkersdorf |
| 2008 | FPL | Network processors. | Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf |
| 2007 | DSD | Power Estimation of Time Variant SoCs with TAPES. | Andreas Lankes, Thomas Wild, Johannes Zeppenfeld |
| 2006 | DATE | Performance evaluation for system-on-chip architectures using trace-based transaction level simulation. | Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf |
| 2003 | DSD | A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges. | Winthir Brunnbauer, Thomas Wild, Jrgen Foag, Nuria Pazos |
| 2003 | VLSID | Mapping and Scheduling for Architecture Exploration of Networking SoCs. | Thomas Wild, Jrgen Foag, Nuria Pazos, Winthir Brunnbauer |
| 2002 | ISCC | Predictive methodology for high-performance networking. | Jrgen Foag, Thomas Wild, Nuria Pazos, Winthir Brunnbauer |