Skip to content

Tulika Mitra

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

115

Venues

37

Active years

1997–2026

Best venue rank

A*

Where they publish

Papers

115 indexed papers, newest first.

YearVenueTitleAuthors
2026AAAICondensed Data Expansion Using Model Inversion for Knowledge Distillation.Kuluhan Binici, Shivam Aggarwal, Cihan Acar, Nam Trung Pham, Karianto Leman, Gim Hee Lee, Tulika Mitra
2026AAAIHALO: Hardware-Aware Quantization with Low Critical-Path-Delay Weights for LLM Acceleration.Rohan Juneja, Shivam Aggarwal, Safeen Huda, Tulika Mitra, Li-Shiuan Peh
2026ASPLOSA Data-Driven Dynamic Execution Orchestration Architecture.Zhenyu Bai, Pranav Dangi, Rohan Juneja, Zhaoying Li, Zhanglu Yan, Huiying Lan, Tulika Mitra
2025ASPLOSEnhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning.Zhaoying Li, Pranav Dangi, Chenyang Yin, Thilini Kaushalya Bandara, Rohan Juneja, Cheng Tan, Zhenyu Bai, Tulika Mitra
2025DACRewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm.Zhaoying Li, Dan Wu, Dhananjaya Wijerathne, Dan Chen, Huize Li, Cheng Tan, Tulika Mitra
2025DATEHyAtten: Hybrid Photonic-Digital Architecture for Accelerating Attention Mechanism.Huize Li, Dan Chen, Tulika Mitra
2025DATEDAOP: Data-Aware Offloading and Predictive Pre-Calculation for Efficient MoE Inference.Yujie Zhang, Shivam Aggarwal, Tulika Mitra
2025ICCADBuilding an Open CGRA Ecosystem for Agile Innovation.Rohan Juneja, Pranav Dangi, Thilini Kaushalya Bandara, Zhaoying Li, Dhananjaya Wijerathne, Li-Shiuan Peh, Tulika Mitra
2025ICIPEfficient Text-to-Image Generation: An Adaptive Step Schedule Controller for Diffusion Models.Kuluhan Binici, Cihan Acar, Shivam Aggarwal, Siying Liu, Tulika Mitra
2025MICRONexus Machine: An Energy-Efficient Active Message Inspired Reconfigurable Architecture.Rohan Juneja, Pranav Dangi, Thilini Kaushalya Bandara, Tulika Mitra, Li-Shiuan Peh
2024BMVCGeneralizing Teacher Networks for Effective Knowledge Distillation Across Student Architectures.Kuluhan Binici, Weiming Wu, Tulika Mitra
2024DACSWAT: Scalable and Efficient Window Attention-based Transformers Acceleration on FPGAs.Zhenyu Bai, Pranav Dangi, Huize Li, Tulika Mitra
2024DATECRISP: Hybrid Structured Sparsity for Class-Aware Model Pruning.Shivam Aggarwal, Kuluhan Binici, Tulika Mitra
2024FPLShedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs.Shivam Aggarwal, Hans Jakob Damsgaard, Alessandro Pappalardo, Giuseppe Franco, Thomas B. Preuer, Michaela Blott, Tulika Mitra
2024HPCAASADI: Accelerating Sparse Attention Using Diagonal-based In-Situ Computing.Huize Li, Zhaoying Li, Zhenyu Bai, Tulika Mitra
2024ICCADSustainable Hardware Specialization.Pranav Dangi, Thilini Kaushalya Bandara, Saeideh Sheikhpour, Tulika Mitra, Lieven Eeckhout
2024MICROICED: An Integrated CGRA Framework Enabling DVFS-Aware Acceleration.Cheng Tan, Miaomiao Jiang, Deepak Patil, Yanghui Ou, Zhaoying Li, Lei Ju, Tulika Mitra, Hyunchul Park, Antonino Tumeo, Jeff Zhang
2023DATEChameleon: Dual Memory Replay for Online Continual Learning on Edge Devices.Shivam Aggarwal, Kuluhan Binici, Tulika Mitra
2023ICCADFLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow.Thilini Kaushalya Bandara, Dan Wu, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh
2022AAAIRobust and Resource-Efficient Data-Free Knowledge Distillation by Generative Pseudo Replay.Kuluhan Binici, Shivam Aggarwal, Nam Trung Pham, Karianto Leman, Tulika Mitra
2022ASPLOSREVAMP: a systematic framework for heterogeneous CGRA realization.Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh
2022DACPANORAMA: divide-and-conquer approach for mapping complex loop kernels on CGRA.Dhananjaya Wijerathne, Zhaoying Li, Thilini Kaushalya Bandara, Tulika Mitra
2022DATEGraphWave: A Highly-Parallel Compute-at-Memory Graph Processing Accelerator.Jinho Lee, Burin Amornpaisannon, Tulika Mitra, Trevor E. Carlson
2022HPCALISA: Graph Neural Network based Portable Mapping on Spatial Accelerators.Zhaoying Li, Dan Wu, Dhananjaya Wijerathne, Tulika Mitra
2022ICCDPower-Performance Characterization of TinyML Systems.Yujie Zhang, Dhananjaya Wijerathne, Zhaoying Li, Tulika Mitra
2022WACVPreventing Catastrophic Forgetting and Distribution Mismatch in Knowledge Distillation via Synthetic Data.Kuluhan Binici, Nam Trung Pham, Tulika Mitra, Karianto Leman
2021DATEHiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction.Dhananjaya Wijerathne, Zhaoying Li, Anuj Pathania, Tulika Mitra, Lothar Thiele
2021MOBICOMFSA: fronthaul slicing architecture for 5G using dataplane programmable switches.Nishant Budhdev, Raj Joshi, Pravein Govindan Kannan, Mun Choon Chan, Tulika Mitra
2020CoNEXTSlicing 5G fronthaul networks using programmable switches.Nishant Budhdev, Raj Joshi, Pravein Govindan Kannan, Mun Choon Chan, Tulika Mitra
2020DACBrezeFlow: Unified Debugger for Android CPU Power Governors and Schedulers on Edge Devices.Alexander Hoffman, Anuj Pathania, Philipp H. Kindt, Samarjit Chakraborty, Tulika Mitra
2020DATEUnified Thread- and Data-Mapping for Multi-Threaded Multi-Phase Applications on SPM Many-Cores.Vanchinathan Venkataramani, Anuj Pathania, Tulika Mitra
2020ICASSPTime-Predictable Software-Defined Architecture with Sdf-Based Compiler Flow for 5g Baseband Processing.Vanchinathan Venkataramani, Bruno Bodin, Aditi Kulkarni Mohite, Tulika Mitra, Li-Shiuan Peh
2020NetworkingPoster: IsoRAN: Isolation and Scaling for 5G RAN via User-Level Data Plane Virtualization.Nishant Budhdev, Mun Choon Chan, Tulika Mitra
2020RTCSASimultaneous Progressing Switching Protocols for Timing Predictable Real-Time Network-on-Chips.Niklas Ueter, Jian-Jia Chen, Georg von der Brggen, Vanchinathan Venkataramani, Tulika Mitra
2019DACTime-Predictable Computing by Design: Looking Back, Looking Forward.Tulika Mitra
2019DATEPrediction-Based Task Migration on S-NUCA Many-Cores.Martin Rapp, Anuj Pathania, Tulika Mitra, Jrg Henkel
2019ICCAD4D-CGRA: Introducing Branch Dimension to Spatio-Temporal Application Mapping on CGRAs.Manupa Karunaratne, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh
2018DACDnestmap: mapping deeply-nested loops on ultra-low power CGRAs.Manupa Karunaratne, Cheng Tan, Aditi Kulkarni Mohite, Tulika Mitra, Li-Shiuan Peh
2018DACQoS-aware stochastic power management for many-cores.Anuj Pathania, Heba Khdr, Muhammad Shafique, Tulika Mitra, Jrg Henkel
2018INFOCOMPRNishant Budhdev, Mun Choon Chan, Tulika Mitra
2018ISCAStitch: Fusible Heterogeneous Accelerators Enmeshed with Many-Core Architecture for Wearables.Cheng Tan, Manupa Karunaratne, Tulika Mitra, Li-Shiuan Peh
2017DACHyCUBE: A CGRA with Reconfigurable Single-cycle Multi-hop Interconnect.Manupa Karunaratne, Aditi Kulkarni Mohite, Tulika Mitra, Li-Shiuan Peh
2017DATEScalable probabilistic power budgeting for many-cores.Anuj Pathania, Heba Khdr, Muhammad Shafique, Tulika Mitra, Jrg Henkel
2017DATEDesign Space exploration of FPGA-based accelerators with multi-level parallelism.Guanwen Zhong, Alok Prakash, Siqi Wang, Yun Liang, Tulika Mitra, Smal Niar
2017PDPA Rapid Data Communication Exploration Tool for Hybrid CPU-FPGA Architectures.Mariem Makni, Smal Niar, Mouna Baklouti, Guanwen Zhong, Tulika Mitra, Mohamed Abid
2016CASESLOCUS: low-power customizable many-core architecture for wearables.Cheng Tan, Aditi Kulkarni Mohite, Vanchinathan Venkataramani, Manupa Karunaratne, Tulika Mitra, Li-Shiuan Peh
2016DACDistributed scheduling for many-cores using cooperative game theory.Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra, Jrg Henkel
2016DACImproving mobile gaming performance through cooperative CPU-GPU thermal management.Alok Prakash, Hussam Amrouch, Muhammad Shafique, Tulika Mitra, Jrg Henkel
2016DACLin-analyzer: a high-level performance analysis tool for FPGA-based accelerators.Guanwen Zhong, Alok Prakash, Yun Liang, Tulika Mitra, Smal Niar
2016DATEDistributed fair scheduling for many-cores.Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra, Jrg Henkel
2016ICSEfficient Timestamp-Based Cache Coherence Protocol for Many-Core Architectures.Yuan Yao, Guanhua Wang, Zhiguo Ge, Tulika Mitra, Wenzhi Chen, Naxin Zhang
2016ICSEAutomated partitioning of android applications for trusted execution environments.Konstantin Rubinov, Lucia Rosculete, Tulika Mitra, Abhik Roychoudhury
2015ASPDACApproximation-aware scheduling on heterogeneous multi-core architectures.Cheng Tan, Thannirmalai Somu Muthukaruppan, Tulika Mitra, Lei Ju
2015CGOImproving GPGPU energy-efficiency through concurrent kernel execution and DVFS.Qing Jiao, Mian Lu, Huynh Phung Huynh, Tulika Mitra
2015DACPower-Performance Modelling of Mobile Gaming Workloads on Heterogeneous MPSoCs.Anuj Pathania, Alexandru Eugen Irimiea, Alok Prakash, Tulika Mitra
2015DATESelectDirectory: a selective directory for cache coherence in many-core architectures.Yuan Yao, Guanhua Wang, Zhiguo Ge, Tulika Mitra, Wenzhi Chen, Naxin Zhang
2015ICCDEnergy-efficient execution of data-parallel applications on heterogeneous mobile platforms.Alok Prakash, Siqi Wang, Alexandru Eugen Irimiea, Tulika Mitra
2014ASPLOSPrice theory based power management for heterogeneous multi-cores.Thannirmalai Somu Muthukaruppan, Anuj Pathania, Tulika Mitra
2014DACIntegrated CPU-GPU Power Management for 3D Mobile Games.Anuj Pathania, Qing Jiao, Alok Prakash, Tulika Mitra
2014DATEWCET-Centric dynamic instruction cache locking.Huping Ding, Yun Liang, Tulika Mitra
2014ICCDDesign space exploration of multiple loops on FPGAs using high level synthesis.Guanwen Zhong, Vanchinathan Venkataramani, Yun Liang, Tulika Mitra, Smal Niar
2013ASPDACShared cache aware task mapping for WCRT minimization.Huping Ding, Yun Liang, Tulika Mitra
2013CASESPower-performance modeling on asymmetric multi-cores.Mihai Pricopi, Thannirmalai Somu Muthukaruppan, Vanchinathan Venkataramani, Tulika Mitra, Sanjay Vishin
2013DACIntegrated instruction cache analysis and locking in multitasking real-time systems.Huping Ding, Yun Liang, Tulika Mitra
2013DACHierarchical power management for asymmetric multi-core in dark silicon era.Thannirmalai Somu Muthukaruppan, Mihai Pricopi, Vanchinathan Venkataramani, Tulika Mitra, Sanjay Vishin
2013ICCADA just-in-time customizable processor.Liang Chen, Joseph Tarango, Tulika Mitra, Philip Brisk
2013ICCDEnergy-aware synthesis of application specific MPSoCs.Thannirmalai Somu Muthukaruppan, Haris Javaid, Tulika Mitra, Sri Parameswaran
2013VLSIDLifetime Reliability Aware Architectural Adaptation.Thannirmalai Somu Muthukaruppan, Tulika Mitra
2012DACWCET-centric partial instruction cache locking.Huping Ding, Yun Liang, Tulika Mitra
2012DATEOnline scheduling for multi-core shared reconfigurable fabric.Liang Chen, Thomas Marconi, Tulika Mitra
2011DACShared reconfigurable fabric for multi-core customization.Liang Chen, Tulika Mitra
2010CASESImproved procedure placement for set associative caches.Yun Liang, Tulika Mitra
2010DACInstruction cache locking using temporal reuse profile.Yun Liang, Tulika Mitra
2010SCOPESModeling shared cache and bus in multi-cores for timing analysis.Sudipta Chattopadhyay, Abhik Roychoudhury, Tulika Mitra
2009DACEvaluating design trade-offs in customizable processors.Unmesh D. Bordoloi, Huynh Phung Huynh, Samarjit Chakraborty, Tulika Mitra
2009DACGenerating test programs to cover pipeline interactions.Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra
2009DACA DVS-based pipelined reconfigurable instruction memory.Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
2009DACDynamic thermal management via architectural adaptation.Ramkumar Jayaseelan, Tulika Mitra
2009DATERuntime reconfiguration of custom instructions for real-time embedded systems.Huynh Phung Huynh, Tulika Mitra
2009EMSOFTProbabilistic modeling of data cache behavior.Vinayak Puranik, Tulika Mitra, Y. N. Srikant
2009ICCADA hybrid local-global approach for multi-core thermal management.Ramkumar Jayaseelan, Tulika Mitra
2009VLSIDTemperature Aware Scheduling for Embedded Processors.Ramkumar Jayaseelan, Tulika Mitra
2009RTSSTiming Analysis of Concurrent Programs Running on Shared Cache Multi-Cores.Yan Li, Vivy Suhendra, Yun Liang, Tulika Mitra, Abhik Roychoudhury
2008DACCache modeling in probabilistic execution time analysis.Yun Liang, Tulika Mitra
2008DACExploring locking & partitioning for predictable shared caches on multi-cores.Vivy Suhendra, Tulika Mitra
2008ICCADTemperature aware task sequencing and voltage scaling.Ramkumar Jayaseelan, Tulika Mitra
2007ASPDACA Retargetable Software Timing Analyzer Using Architecture Description Language.Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra, Xu Cheng
2007CASESAn efficient framework for dynamic reconfiguration of instruction-set customization.Huynh Phung Huynh, Joon Edward Sim, Tulika Mitra
2007DATEInstruction-set customization for real-time embedded systems.Huynh Phung Huynh, Tulika Mitra
2007ECRTSCache-Aware Timing Analysis of Streaming Applications.Samarjit Chakraborty, Tulika Mitra, Abhik Roychoudhury, Lothar Thiele, Unmesh D. Bordoloi, Cem Derdiyok
2007FPLDisjoint Pattern Enumeration for Custom Instructions Identification.Pan Yu, Tulika Mitra
2006CASESIntegrated scratchpad memory optimization and task scheduling for MPSoC architectures.Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitra
2006DACExploiting forwarding to improve data bandwidth of instruction-set extensions.Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra
2006DACEfficient detection and exploitation of infeasible paths for software timing analysis.Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen
2006VLSIDHandling Constraints in Multi-Objective GA for Embedded System Design.Biman Chakraborty, Ting Chen, Tulika Mitra, Abhik Roychoudhury
2006RTASEstimating the Worst-Case Energy Consumption of Embedded Software.Ramkumar Jayaseelan, Tulika Mitra, Xianfeng Li
2005ICDCITAnalyzing Loop Paths for Execution Time Estimation.Abhik Roychoudhury, Tulika Mitra, Hemendra Singh Negi
2005RTSSWCET Centric Data Allocation to Scratchpad Memory.Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen
2004CASESScalable custom instructions identification for instruction-set extensible processors.Pan Yu, Tulika Mitra
2004DACCharacterizing embedded applications for instruction-set extensible processors.Pan Yu, Tulika Mitra
2004ICCADConfiguration bitstream compression for dynamically reconfigurable FPGAs.Lei He, Tulika Mitra, Weng-Fai Wong
2004ICSDesign space exploration of caches using compressed traces.Xianfeng Li, Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudhury
2004RTSSModeling Out-of-Order Processors for Software Timing Analysis.Xianfeng Li, Abhik Roychoudhury, Tulika Mitra
2003DACAccurate timing analysis by modeling caches, speculation and their interaction.Xianfeng Li, Tulika Mitra, Abhik Roychoudhury
2003DATEUsing Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol.Abhik Roychoudhury, Tulika Mitra, S. R. Karri
2003DCCCompression-Domain Editing of 3D Models.Tulika Mitra, Tzi-cker Chiueh
2003FPLA Model for Hardware Realization of Kernel Loops.Jirong Liao, Weng-Fai Wong, Tulika Mitra
2003PPoPPCompactly representing parallel program executions.Ankit Goel, Abhik Roychoudhury, Tulika Mitra
2002FCCMAn FPGA Implementation of Triangle Mesh Decompression.Tulika Mitra, Tzi-cker Chiueh
2002ICSESpecifying multithreaded Java semantics for program verification.Abhik Roychoudhury, Tulika Mitra
2002USENIXA Decoupled Architecture for Application-Specific File Prefetching.Chuan-Kai Yang, Tulika Mitra, Tzi-cker Chiueh
1999ISCADynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs.Sriram Vajapeyam, P. J. Joseph, Tulika Mitra
1999MICRODynamic 3D Graphics Workload Characterization and the Architectural Implications.Tulika Mitra, Tzi-cker Chiueh
1998ICPADSImplementation and Evaluation of the Parallel Mesa Library.Tulika Mitra, Tzi-cker Chiueh
1997ISCAImproving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences.Sriram Vajapeyam, Tulika Mitra