Valentin Gherman
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
18
Venues
5
Active years
2004–2025
Best venue rank
B
Where they publish
Papers
18 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | IOLTS | Improving Error Correction with Weak-Bit Information in Resistive Memories. | Valentin Gherman, Giuseppe Piccolboni, Zeev Freidin, Matan Guttman, Amir Regev, Gabriel Molas, Ishai Naveh, Bastien Giraud, Antoine Hebert, Ilan Sever |
| 2024 | VTS | Sequential Decoders for Binary Linear Block ECCs. | Valentin Gherman, Cyrille Laffond |
| 2020 | DATE | Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities. | Valentin Gherman, Samuel Evain, Bastien Giraud |
| 2017 | ETS | Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps. | Marcelino Seif, Emna Farjallah, Franck Badets, Emna Chabchoub, Christophe Layer, Jean-Marc Armani, Francis Joffre, Costin Anghel, Luigi Dilillo, Valentin Gherman |
| 2017 | ITC | Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics. | Valentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo |
| 2014 | ETS | Shadow-scan design with low latency overhead and in-situ slack-time monitoring. | Sbastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner, Valentin Gherman |
| 2014 | IOLTS | Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths. | Sbastien Sarrazin, Samuel Evain, Ivan Miro Panades, Lirida Alves de Barros Naviner, Valentin Gherman |
| 2013 | DATE | Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection. | Sbastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman |
| 2013 | ETS | Error-correction schemes with erasure information for fast memories. | Samuel Evain, Valentin Gherman |
| 2012 | ETS | Memory reliability improvements based on maximized error-correcting codes. | Valentin Gherman, Samuel Evain, Yannick Bonhomme |
| 2011 | DATE | Error prediction based on concurrent self-test and reduced slack time. | Valentin Gherman, J. Massas, Samuel Evain, Stphane Chevobbe, Yannick Bonhomme |
| 2011 | IOLTS | Generalized parity-check matrices for SEC-DED codes with fixed parity. | Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme |
| 2011 | VTS | Programmable extended SEC-DED codes for memory errors. | Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme |
| 2010 | IOLTS | Programmable restricted SEC codes to mask permanent faults in semiconductor memories. | Samuel Evain, Yannick Bonhomme, Valentin Gherman |
| 2009 | DATE | System-level hardware-based protection of memories against soft-errors. | Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme |
| 2006 | ETS | Deterministic Logic BIST for Transition Fault Testing. | Valentin Gherman, Hans-Joachim Wunderlich, Jrgen Schlffel, Michael Garbers |
| 2005 | VTS | Implementing a Scheme for External Deterministic Self-Test. | Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jrgen Schlffel |
| 2004 | ITC | Efficient Pattern Mapping for Deterministic Logic BIST. | Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers |