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Venkatesh Akella

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

29

Venues

21

Active years

1992–2025

Best venue rank

A*

Where they publish

Papers

29 indexed papers, newest first.

YearVenueTitleAuthors
2025HPCANOVA: A Novel Vertex Management Architecture for Scalable Graph Processing.Marjan Fariborz, Mahyar Samani, Austin York, S. J. Ben Yoo, Jason Lowe-Power, Venkatesh Akella
2025SCTEGRA - Scaling Up Graph Processing with Disaggregated Computing.William Shaddix, Mahyar Samani, Jason Lowe-Power, Venkatesh Akella
2021ISPASSA Case Against Hardware Managed DRAM Caches for NVRAM Based Systems.Mark Hildebrand, Julian T. Angeles, Jason Lowe-Power, Venkatesh Akella
2020ASPLOSAutoTM: Automatic Tensor Movement in Heterogeneous Memory Systems using Integer Linear Programming.Mark Hildebrand, Jawad Khan, Sanjeev Trika, Jason Lowe-Power, Venkatesh Akella
2020ICPPHCAPP: Scalable Power Control for Heterogeneous 2.5D Integrated Systems.Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella
2018HiPCImproving Provisioned Power Efficiency in HPC Systems with GPU-CAPP.Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella
2018ISCAA case for exposing extra-architectural state in the ISA: position paper.Jason Lowe-Power, Venkatesh Akella, Matthew K. Farrens, Samuel T. King, Christopher J. Nitta
2017HPCADesign and Evaluation of AWGR-Based Photonic NoC Architectures for 2.5D Integrated High Performance Computing Systems.Paolo Grani, Roberto Proietti, Venkatesh Akella, S. J. Ben Yoo
2017ICCDImproving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing.Kramer Straube, Christopher Nitta, Raj Amirtharajah, Matthew K. Farrens, Venkatesh Akella
2016ASPDACDesign space exploration of FPGA-based Deep Convolutional Neural Networks.Mohammad Motamedi, Philipp Gysel, Venkatesh Akella, Soheil Ghiasi
2016ICDMHogWild++: A New Mechanism for Decentralized Asynchronous Stochastic Gradient Descent.Huan Zhang, Cho-Jui Hsieh, Venkatesh Akella
2013ISLPEDUpdate rate tradeoffs for improving online power modeling in smartphones.Frank Maker III, Rajeevan Amirtharajah, Venkatesh Akella
2011HPCAAddressing system-level trimming issues in on-chip nanophotonic networks.Christopher Nitta, Matthew K. Farrens, Venkatesh Akella
2011MICROResilient microring resonator based photonic networks.Christopher Nitta, Matthew K. Farrens, Venkatesh Akella
2009DATEAccelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing.Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella
2009EMSOFTMarkov decision process (MDP) framework for optimizing software on mobile phones.Tang Lung Cheung, Kari Okamoto, Frank Maker III, Xin Liu, Venkatesh Akella
2008HOTIOCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects.Amit Hadke, Tony Benavides, S. J. Ben Yoo, Rajeevan Amirtharajah, Venkatesh Akella
2008ICCDDesign and evaluation of an optical CPU-DRAM interconnect.Amit Hadke, Tony Benavides, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella
2006HiPCSegmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns.Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella
2005ICASSPComplexity metric driven energy optimization framework for implementing MPEG-21 scalable video decoders.Gouri Landge, Mihaela van der Schaar, Venkatesh Akella
2004ICIPRate-distortion-complexity adaptive video compression and streaming.Mihaela van der Schaar, Deepak S. Turaga, Venkatesh Akella
2004ISCASynchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor.John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong
2004SPAAEfficient orchestration of sub-word parallelism in media processors.John Y. Oliver, Venkatesh Akella, Frederic T. Chong
2003FPLImproving DSP Performance with a Small Amount of Field Programmable Logic.John Y. Oliver, Venkatesh Akella
1999VLSIDAutomatic Insertion of Gated Clocks at Register Transfer Level.Nithya Raghavan, Venkatesh Akella, Smita Bakshi
1995ICCDAsynchronous 2-D discrete cosine transform core processor.Bret Stott, Dave Johnson, Venkatesh Akella
1994ICCDPerformance Analysis and Optimization of Asynchronous Circuits.Prabhakar Kudva, Ganesh Gopalakrishnan, Erik Brunvand, Venkatesh Akella
1992ICCADSHILPA: a high-level synthesis system for self-timed circuits.Venkatesh Akella, Ganesh Gopalakrishnan
1992VLSIDFrom Process-Oriented Functional Specifications to Efficient Asynchronous Circuits.Venkatesh Akella, Ganesh Gopalakrishnan