| 2026 | ASPDAC | A Scalable and High-Quality Qubit Mapping and Shuttling Framework for Neutral Atom Quantum Devices. | Sung-Ying Hsieh, Wai-Kei Mak |
| 2026 | ASPDAC | An Effective Placement Framework for Designs with Half-Row-Extended Cells. | Po-Yi Wu, Tzu-Sheng Hung, Wai-Kei Mak, Ting-Chi Wang |
| 2025 | ICCAD | An Efficient Routing Optimization Framework for Silicon-Based Spin-Qubit Devices. | Ching-Yao Huang, Wai-Kei Mak |
| 2024 | ASPDAC | CTQr: Control and Timing-Aware Qubit Routing. | Ching-Yao Huang, Wai-Kei Mak |
| 2024 | ASPDAC | Row Planning and Placement for Hybrid-Row-Height Designs. | Ching-Yao Huang, Wai-Kei Mak |
| 2024 | ASPDAC | An Effective Netlist Planning Approach for Double-sided Signal Routing. | Tzu-Chuan Lin, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang |
| 2024 | ICCAD | An Effective ECO Methodology for Reducing Back-side Design Rule Violations in Double-sided Signal Routing. | Che-Ping Tsai, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang |
| 2022 | ASPDAC | HybridGP: Global Placement for Hybrid-Row-Height Designs. | Kuan-Yu Chen, Hsiu-Chu Hsu, Wai-Kei Mak, Ting-Chi Wang |
| 2022 | ICCAD | Reinforcement Learning and DEAR Framework for Solving the Qubit Mapping Problem. | Ching-Yao Huang, Chi-Hsiang Lien, Wai-Kei Mak |
| 2022 | ICCAD | Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization. | Meng-Yun Liu, Yu-Cheng Lai, Wai-Kei Mak, Ting-Chi Wang |
| 2021 | ASPDAC | Manufacturing-Aware Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement Refinement. | Yu-Jin Xie, Kuan-Yu Chen, Wai-Kei Mak |
| 2021 | ICCAD | A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits. | Ching-Cheng Wang, Wai-Kei Mak |
| 2018 | ICCAD | A practical detailed placement algorithm under multi-cell spacing constraints. | Yu-Hsiang Cheng, Ding-Wei Huang, Wai-Kei Mak, Ting-Chi Wang |
| 2017 | ASPDAC | Optimizing DSA-MP decomposition and redundant via insertion with dummy vias. | Chung-Yao Hung, Peng-Yi Chou, Wai-Kei Mak |
| 2017 | ICCAD | Making split fabrication synergistically secure and manufacturable. | Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran |
| 2017 | ICCAD | Making split fabrication synergistically secure and manufacturable. | Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran |
| 2016 | ASPDAC | Minimum implant area-aware placement and threshold voltage refinement. | Seong-I Lei, Wai-Kei Mak, Chris Chu |
| 2016 | DAC | Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration. | Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak |
| 2015 | ASPDAC | A fast parallel approach for common path pessimism removal. | Chung-Hao Tsai, Wai-Kei Mak |
| 2015 | DAC | Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography. | Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak |
| 2014 | ASPDAC | Flexible packed stencil design with multiple shaping apertures for e-beam lithography. | Chris Chu, Wai-Kei Mak |
| 2014 | ASPDAC | A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules. | Sheng-Kai Wu, Po-Yi Hsu, Wai-Kei Mak |
| 2014 | DAC | Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout. | Yixiao Ding, Chris Chu, Wai-Kei Mak |
| 2013 | ASPDAC | A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules. | Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen |
| 2011 | ASPDAC | Cut-demand based routing resource allocation and consolidation for routability enhancement. | Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak |
| 2011 | FPL | Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign. | Seong-I Lei, Wai-Kei Mak |
| 2009 | ASPDAC | Signal skew aware floorplanning and bumper signal assignment technique for flip-chip. | Cheng-Yu Wang, Wai-Kei Mak |
| 2009 | ICCAD | How to consider shorts and guarantee yield rate improvement for redundant wire insertion. | Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak |
| 2009 | ICCAD | Pad assignment for die-stacking System-in-Package design. | Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang |
| 2007 | ASPDAC | Voltage Island Generation under Performance Requirement for SoC Designs. | Wai-Kei Mak, Jr-Wei Chen |
| 2006 | ASPDAC | A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers. | Chien-Chang Chen, Wai-Kei Mak |
| 2005 | ASPDAC | Modern FPGA constrained placement. | Wai-Kei Mak |
| 2003 | ASPDAC | Efficient LUT-based FPGA technology mapping for power minimization. | Hao Li, Wai-Kei Mak, Srinivas Katkoori |
| 2003 | FPGA | I/O placement for FPGAs with multiple I/O standards. | Wai-Kei Mak |
| 1999 | ISCAS | A fast hypergraph minimum cut algorithm. | Wai-Kei Mak, D. F. Wong |
| 1998 | FPGA | Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). | Wai-Kei Mak, D. F. Wong |
| 1998 | ICCD | Performance-driven board-level routing for FPGA-based logic emulation. | Wai-Kei Mak, D. F. Wong |
| 1997 | ICCD | Channel Segmentation Design for Symmentrical FPGAs. | Wai-Kei Mak, D. F. Wong |
| 1996 | ICCAD | Minimum replication min-cut partitioning. | Wai-Kei Mak, D. F. Wong |
| 1995 | DAC | On Optimal Board-Level Routing for FPGA-Based Logic Emulation. | Wai-Kei Mak, D. F. Wong |
| 1995 | ICCAD | Board-level multi-terminal net routing for FPGA-based logic emulation. | Wai-Kei Mak, D. F. Wong |
| 1990 | USENIX | Implementation of the Ficus Replicated File System. | Richard G. Guy, John S. Heidemann, Wai-Kei Mak, Thomas W. Page Jr., Gerald J. Popek, Dieter Rothmeier |