| 2015 | DDECS | TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms. | Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier |
| 2010 | DDECS | Fault diagnosis of crosstalk induced glitches and delay faults. | Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier |
| 2010 | VLSID | Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults. | Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier |
| 2009 | ICCAD | Timing Arc based logic analysis for false noise reduction. | Murthy Palla, Jens Bargfrede, Stephan Eggersgl, Walter Anheier, Rolf Drechsler |
| 2007 | DDECS | XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects. | Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier |
| 2006 | ICCD | Reduction of Crosstalk Pessimism using Tendency Graph Approach. | Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier |
| 2005 | VLSID | ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. | Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jrgen Schlffel |
| 1999 | ETS | On random pattern testability of cryptographic VLSI cores. | Andreas Schubert, Walter Anheier |
| 1998 | VLSID | A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech Signal. | Ansgar Drolshagen, Walter Anheier, C. Chandra Sekhar |
| 1995 | ICCD | Distributed automatic test pattern generation with a parallel FAN algorithm. | Stefan Radtke, Jens Bargfrede, Walter Anheier |
| 1994 | ISCAS | A New Strategy for Test Pattern Generation in Sequential Circuits. | Beom-Ik Cheon, Walter Anheier, Rainer Laur |
| 1994 | MVA | Segmentation of Scanned Maps in Uniform Color Spaces. | Bernd Lauterbach, Walter Anheier |