| 2013 | DAC | Post-placement voltage island generation for timing-speculative circuits. | Rong Ye, Feng Yuan, Zelong Sun, Wen-Ben Jone, Qiang Xu |
| 2013 | DAC | On testing timing-speculative circuits. | Feng Yuan, Yannan Liu, Wen-Ben Jone, Qiang Xu |
| 2010 | ICCAD | Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping. | Hao Xu, Wen-Ben Jone, Ranga Vemuri |
| 2010 | ICCAD | Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs. | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
| 2010 | VLSID | Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. | Hao Xu, Wen-Ben Jone, Ranga Vemuri |
| 2009 | DATE | Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
| 2009 | ICCAD | Temporal and spatial idleness exploitation for optimal-grained leakage control. | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
| 2008 | ICCAD | Accurate energy breakeven time estimation for run-time power gating. | Hao Xu, Wen-Ben Jone, Ranga Vemuri |
| 2008 | ICCD | Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
| 2008 | ISLPED | Dynamic virtual ground voltage estimation for power gating. | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
| 2008 | ITC | Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. | Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li |
| 2007 | ICCD | An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects. | Jianxun Liu, Wen-Ben Jone |
| 2006 | DAC | DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip. | Ming Li, Qing-An Zeng, Wen-Ben Jone |
| 2006 | ITC | Fault Modeling and Detection for Drowsy SRAM Caches. | Wei Pei, Wen-Ben Jone, Yiming Hu |
| 2005 | ASPDAC | Design and design automation of rectification logic for engineering change. | Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone |
| 2004 | ISCAS | Phased tag cache: an efficient low power cache system. | Rui Min, Wen-Ben Jone, Yiming Hu |
| 2004 | ISLPED | Location cache: a low-power L2 cache system. | Rui Min, Wen-Ben Jone, Yiming Hu |
| 2004 | VLSID | Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs. | Rui Min, Zhiyong Xu, Yiming Hu, Wen-Ben Jone |
| 2004 | VTS | A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices. | Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone |
| 2001 | VLSID | An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers. | Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das |
| 2001 | VLSID | A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers. | Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das |
| 2000 | ICCAD | Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. | Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang |
| 1999 | DAC | Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. | Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone |
| 1999 | ISCAS | Power reduction through iterative gate sizing and voltage scaling. | Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone |
| 1999 | VTS | An Efficient BIST Method for Small Buffers. | Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee |
| 1998 | ITC | A novel combinational testability analysis by considering signal correlation. | Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai |
| 1998 | ITC | A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. | Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu |
| 1998 | VLSID | A Stochastic Method for Defect Level Analysis of Pseudorandom Testing. | Wen-Ben Jone, Sunil R. Das |
| 1997 | VLSID | Delay Fault Coverage Enhancement Using Multiple Test Observation Times. | Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das |
| 1996 | VLSID | Syndrome signature in output compaction for VLSI BIST. | Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak |
| 1995 | VLSID | An improved output compaction technique for built-in self-test in VLSI circuits. | Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak |
| 1994 | ICPADS | Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered Approach. | Amiya R. Nayak, Wen-Ben Jone, Sunil R. Das |
| 1994 | VLSID | On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition. | Sunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi |
| 1993 | DAC | Timing Optimization By Gate Resizing And Critical Path Identification. | Wen-Ben Jone, Chen-Liang Fang |
| 1993 | ISCAS | On Multiple Fault Detection of Parity Checkers. | Cheng-Juei Wu, Wen-Ben Jone |
| 1993 | ITC | Realizing a High Measure of Confidence for Defect Level Analysis of Random Testing. | Paresh Gondalia, Allan Gutjahr, Wen-Ben Jone |
| 1993 | VLSID | CACOP - A Random Pattern Testability Analyzer. | Wen-Ben Jone, Sunil R. Das |
| 1991 | ICCD | Reduced Hamming Count and Its Aliasing Probability. | Anita Gleason, Wen-Ben Jone |
| 1991 | ITC | Defect Level Estimation of Random and Pseudorandom Testing. | Wen-Ben Jone |
| 1989 | DAC | A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing. | Wen-Ben Jone, Christos A. Papachristou |
| 1989 | DAC | A Scheme for Overlaying Concurrent Testing of VLSI Circuits. | Wen-Ben Jone, Christos A. Papachristou, M. Pereira |
| 1989 | ICCD | Hamming count-a compaction testing technique. | Anita Gleason, Wen-Ben Jone |