| 2026 | DDECS | A 320.3 fj/Bit UCIe Advanced Package TX Driver in 28 nm FDSOI. | Patryk Kozicki, Viki Szortyka, Witold A. Pleskacz |
| 2026 | DDECS | CAD Software for the Detection of Floating Metals for Advanced CMOS Technologies. | Sweekriti Patle, Marika Grochowska, Witold A. Pleskacz |
| 2024 | DDECS | The Impact of Well-Edge Proximity Effect on PMOS Threshold Voltage in Various Submicron CMOS Technologies. | Marika Grochowska, Witold A. Pleskacz |
| 2020 | DDECS | CMOS Differential Amplifier as a Physically Unclonable Function. | Szymon Reszewicz, Krzysztof Siwiec, Witold A. Pleskacz |
| 2019 | DDECS | Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter. | Mariusz Derlecki, Krzysztof Siwiec, Pawel Narczyk, Witold A. Pleskacz |
| 2019 | ITC | International Symposium on Design and Diagnostics of Electronic Circuits and Systems. | Zoran Stamenkovic, Alberto Bosio, Gyrgy Cserey, Ondrej Novk, Witold A. Pleskacz, Luks Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjakov |
| 2018 | DDECS | 2.4 GHz LC-VCO with Improved Robustness against PVT Using FD-SOI Body Biasing Technique. | Szymon Reszewicz, Krzysztof Siwiec, Witold A. Pleskacz |
| 2017 | DDECS | Analog front-end for precise human body temperature measurement. | Pawel Narczyk, Krzysztof Siwiec, Witold A. Pleskacz |
| 2016 | DDECS | Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology. | Igor Butryn, Krzysztof Siwiec, Jakub Kopanski, Witold A. Pleskacz |
| 2016 | DDECS | Precision human body temperature measurement based on thermistor sensor. | Pawel Narczyk, Krzysztof Siwiec, Witold A. Pleskacz |
| 2016 | DDECS | BioSoC: Highly integrated System-on-Chip for health monitoring. | Krzysztof Siwiec, Krzysztof Marcinek, Piotr Boguszewicz, Tomasz Borejko, Aleh Halauko, Adam Jarosz, Jakub Kopanski, Ewa Kurjata-Pfitzner, Pawel Narczyk, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz |
| 2015 | DDECS | A Low Ripple Current Mode Voltage Doubler. | Andrzej Grodzicki, Witold A. Pleskacz |
| 2015 | DDECS | Implementation of the ADELITE Microcontroller for Biomedical Applications. | Krzysztof Marcinek, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz |
| 2015 | DDECS | UVM-based Verification of Bluetooth Low Energy Controller. | Maciej Moskala, Patryk Kloczko, Marek Cieplucha, Witold A. Pleskacz |
| 2014 | DDECS | Multistage low ripple charge pump. | Andrzej Grodzicki, Witold A. Pleskacz |
| 2013 | DDECS | Intermediate frequency filter calibration method for radio frequency receivers in modern CMOS technologies. | Krzysztof Siwiec, Aleksander Koter, Witold A. Pleskacz |
| 2012 | DDECS | AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems. | Krzysztof Marcinek, Witold A. Pleskacz |
| 2012 | DDECS | LC-VCO design automation tool for nanometer CMOS technology. | Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz |
| 2011 | DDECS | A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology. | Jakub Kopanski, Witold A. Pleskacz, Dariusz Pienkowski |
| 2011 | DDECS | A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations. | Michal Lukaszewicz, Tomasz Borejko, Witold A. Pleskacz |
| 2011 | DDECS | PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications. | Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz |
| 2011 | DDECS | CAD tool for PLL Design. | Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz |
| 2010 | DDECS | A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies. | Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz |
| 2009 | DDECS | Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS. | Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz |
| 2009 | DDECS | MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio. | Peter Malk, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Balz, Witold A. Pleskacz |
| 2009 | DDECS | Enhanced LEON3 core for superscalar processing. | Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz |
| 2008 | DDECS | Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology. | Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjakov |
| 2008 | DDECS | A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations. | Tomasz Borejko, Witold A. Pleskacz |
| 2008 | DDECS | Various MDCT implementations in 0.35m CMOS. | Peter Malk, Marcel Balz, Martin Simlastk, Arkadiusz W. Luczyk, Witold A. Pleskacz |
| 2008 | DDECS | Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures. | Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz |
| 2008 | DSD | Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. | Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz |
| 2007 | DDECS | Layout to Logic Defect Analysis for Hierarchical Test Generation. | Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski |
| 2007 | DDECS | ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing. | Zbigniew Piatek, Jerzy F. Kolodziejski, Witold A. Pleskacz |
| 2007 | DDECS | Power Dissipation in Basic Global Clock Distribution Networks. | Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz |
| 2005 | DSD | Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. | Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz |
| 2005 | ETS | DOT: new deterministic defect-oriented ATPG tool. | Jaan Raik, Raimund Ubar, Joachim Sudbrock, Wieslaw Kuzmicz, Witold A. Pleskacz |
| 2000 | ETS | Hierarchical defect-oriented fault simulation for digital circuits. | Mykola Blyzniuk, T. Cibkov, Elena Gramatov, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar |
| 1997 | DAC | CAD at the Design-Manufacturing Interface. | Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz |
| 1995 | DATE | SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects. | Witold A. Pleskacz, Wieslaw Kuzmicz |