Wolfgang Ecker
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
60
Venues
18
Active years
1993–2026
Best venue rank
A*
Where they publish
Papers
60 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | Validating Formal Hardware Specifications Through Generated Behavioral Models. | Robert Kunzelmann, Zeyad Tahoun, Vinod Bangalore Ganesh, Maximilian Berger, Emil Baerens, Wolfgang Ecker |
| 2026 | ETS | NURSE: A Distributed Architecture for Runtime Fault Management in Processor Designs. | Ashwin Santhosh, Artur Jutman, Endri Kaja, Wolfgang Ecker, Maksim Jenihhin |
| 2025 | DATE | Multi-Partner Project: Advancing the EDA Tools Landscape for the European RISC-V Ecosystem in TRISTAN. | Fatma Jebali, Caaliph Andriamisaina, Mathieu Jan, Wolfgang Ecker, Florian Egert, Bernhard Fischer, Alessio Burrello, Daniele Jahier Pagliari, Sara Vinco, Giuseppe Tagliavini, Ingo Feldner, Andreas Mauderer, Axel Sauer, Arnr Kristmundsson, Alexander Schober, To Bernier, Matti Kyr, Ulf Schlichtmann, Rocco Jonack |
| 2025 | DDECS | Implementation of Dynamic SISD-SIMD Integer Dividers. | Gianluca Radi, Ares Tahiraga, Robert Kunzelmann, Ties Jan Henderikus Kluter, Wolfgang Ecker |
| 2025 | DDECS | Energy-Efficient Neural Network Inference through Golomb-Rice Compression of Activations for Edge Devices. | Mounika Vaddeboina, Alper Yilmazer, Wolfgang Ecker |
| 2025 | FDL | Leveraging Model-Driven Architecture for Efficient Custom Instruction Utilization in Embedded Systems in C and Rust. | Raphael Kunz, Mayuri Bhadra, Lijun Chen, Stephanie Ecker, Wolfgang Ecker |
| 2025 | VLSID | FPUGen: A FrameWork to Generate Custom Floating Point FMA Accelerators on FPGAs. | Himanshu Rai, Aishwarya Sridhar, Wolfgang Ecker, Nanditha Rao |
| 2024 | DATE | A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. | Paul Palomero Bernardo, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Mller, Andreas Koch, Eyck Jentzsch, Axel Sauer, Ingo Feldner, Wolfgang Ecker |
| 2024 | DDECS | PaGoRi:A Scalable Parallel Golomb-Rice Decoder. | Mounika Vaddeboina, Endri Kaja, Alper Yilmazer, Uttal Ghosh, Wolfgang Ecker |
| 2024 | DSD | Optimizing Data Compression: Enhanced Golomb-Rice Encoding with Parallel Decoding Strategies for TinyML Models. | Mounika Vaddeboina, Alper Yilmayer, Wolfgang Ecker |
| 2023 | DAC | G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators. | Saranyu Chattopadhyay, Keerthikumara Devarajegowda, Bihan Zhao, Florian Lonsing, Brandon A. D'Agostino, Ioanna Vavelidou, Vijay Deep Bhatt, Sebastian Prebeck, Wolfgang Ecker, Caroline Trippel, Clark W. Barrett, Subhasish Mitra |
| 2023 | DDECS | Bits, Flips and RISCs. | Nicolas Gerlin, Endri Kaja, Fabian Vargas, Li Lu, Anselm Breitenreiter, Junchao Chen, Markus Ulbricht, Maribel Gomez, Ares Tahiraga, Sebastian Prebeck, Eyck Jentzsch, Milos Krstic, Wolfgang Ecker |
| 2023 | DSD | Parallel Golomb-Rice Decoder with 8-bit Unary Decoding for Weight Compression in TinyML Applications. | Mounika Vaddeboina, Endri Kaja, Alper Yilmayer, Sebastian Prebeck, Wolfgang Ecker |
| 2022 | DATE | The Scale4Edge RISC-V Ecosystem. | Wolfgang Ecker, Peer Adelt, Wolfgang Mller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jrg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz |
| 2022 | ICCAD | Applying GNNs to Timing Estimation at RTL. | Daniela Sanchez Lopera, Wolfgang Ecker |
| 2022 | RSP | A framework that enables systematic analysis of mixed-signal applications on FPGA. | Gabriel Rutsch, Maximilian Groebner, Anthony Sanders, Konrad Maier, Wolfgang Ecker |
| 2021 | DAC | ISA Modeling with Trace Notation for Context Free Property Generation. | Keerthikumara Devarajegowda, Endri Kaja, Sebastian Siegfried Prebeck, Wolfgang Ecker |
| 2020 | DATE | Gap-free Processor Verification by S | Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, Wolfgang Kunz |
| 2020 | DSD | Kamel: IP-XACT compatible intermediate meta-model for IP generation. | Antti Rautakoura, Matti Kyr, Timo D. Hmlinen, Wolfgang Ecker, Esko Pekkarinen, Mikko Teuho |
| 2020 | DSD | Optimized HW/FW Generation from an Abstract Register Interface Model. | Michael Werner, Igli Zeraliu, Zhao Han, Sebastian Siegfried Prebeck, Lorenzo Servadei, Wolfgang Ecker |
| 2019 | DAC | Increasing Soft Error Resilience by Software Transformation. | Michael Werner, Keerthikumara Devarajegowda, Moomen Chaari, Wolfgang Ecker |
| 2019 | DATE | Embedded Systems' Automation following OMG's Model Driven Architecture Vision. | Wolfgang Ecker, Keerthikumara Devarajegowda, Michael Werner, Zhao Han, Lorenzo Servadei |
| 2019 | DATE | Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision. | Lorenzo Servadei, Elena Zennaro, Keerthikumara Devarajegowda, Martin Manzinger, Wolfgang Ecker, Robert Wille |
| 2019 | DATE | Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. | Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra |
| 2019 | DSD | Formal Verification Methodology in an Industrial Setup. | Lorenzo Servadei, Zhao Han, Michael Werner, Wolfgang Ecker, Keerthikumara Devarajegowda |
| 2018 | DSD | A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications. | Elena Zennaro, Lorenzo Servadei, Keerthikumara Devarajegowda, Wolfgang Ecker |
| 2018 | ICTAI | Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning. | Lorenzo Servadei, Elena Zennaro, Keerthikumara Devarajegowda, Wolfgang Ecker, Robert Wille |
| 2017 | ICCAD | Python based framework for HDSLs with an underlying formal semantics: (Invited paper). | Keerthikumara Devarajegowda, Johannes Schreiner, Rainer Findenig, Wolfgang Ecker |
| 2017 | RSP | The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. | Daniel Mueller-Gritschneder, Keerthikumara Devarajegowda, Martin Dittrich, Wolfgang Ecker, Marc Greim, Ulf Schlichtmann |
| 2016 | DSD | Efficient Checkpointing-Based Safety-Verification Flow Using Compiled-Code Simulation. | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello |
| 2016 | DSN | Transformation of Failure Propagation Models into Fault Trees for Safety Evaluation Purposes. | Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, Bogdan-Andrei Tabacaru |
| 2016 | FDL | Fault-effect analysis on system-level hardware modeling using virtual prototypes. | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello |
| 2016 | ICCAD | Where formal verification can help in functional safety analysis. | Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann |
| 2016 | SAFECOMP | Gate-Level-Accurate Fault-Effect Analysis at Virtual-Prototype Speed. | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello |
| 2015 | DAC | A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems. | Moomen Chaari, Wolfgang Ecker, Cristiano Novello, Bogdan-Andrei Tabacaru, Thomas Kruse |
| 2015 | DATE | The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems. | Oliver Bringmann, Wolfgang Ecker, Andreas Gerstlauer, Ajay Goyal, Daniel Mueller-Gritschneder, Prasanth Sasidharan, Simranjit Singh |
| 2014 | ASPDAC | A transaction-oriented UVM-based library for verification of analog behavior. | Alexander W. Rath, Volkan Esen, Wolfgang Ecker |
| 2014 | DAC | Metasynthesis for Designing Automotive SoCs. | Wolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal |
| 2014 | DAC | Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. | Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Grttner, Thomas Kruse, Christoph Kuznik, Hoang Minh Le, Andreas Mauderer, Wolfgang Mller, Daniel Mller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl |
| 2014 | DATE | The metamodeling approach to system level synthesis. | Wolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal |
| 2010 | DATE | Panel Session - Who Is Closing the embedded software design gap? | Wolfgang Ecker, Pierre Bricaud, Rainer Dmer, Yossi Veller, Stefan Heinen, Jrgen Mssinger, Andreas von Schwerin |
| 2010 | DATE | TLM+ modeling of embedded HW/SW systems. | Wolfgang Ecker, Volkan Esen, Robert Schwencker, Thomas Steininger, Michael Velten |
| 2009 | ASPDAC | Using a dataflow abstracted virtual prototype for HdS-design. | Wolfgang Ecker, Stefan Heinen, Michael Velten |
| 2008 | DATE | Industrial IP Integration Flows based on IP-XACT Standards. | Wido Kruijtzer, Pieter van der Wolf, Erwin A. de Kock, Jan Stuyt, Wolfgang Ecker, Albrecht Mayer, Serge Hustin, Christophe Amerijckx, Serge de Paoli, Emmanuel Vaumorin |
| 2007 | DATE | Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. | Wolfgang Ecker, Volkan Esen, Lars Schnberg, Thomas Steininger, Michael Velten, Michael Hull |
| 2007 | DATE | Interactive presentation: Implementation of a transaction level assertion framework in SystemC. | Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull |
| 2006 | FDL | Case Study on Transaction Level Modeling. | Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten |
| 2006 | FDL | IP Library For Temporal SystemC Assertions. | Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Jacob Smit |
| 2006 | ICCD | Requirements and Concepts for Transaction Level Assertions. | Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten |
| 2006 | MEMOCODE | Execution semantics and formalisms for multi-abstraction TLM assertions. | Wolfgang Ecker, Volkan Esen, Michael Hull |
| 2005 | GI | Evolution of Paradigm Shifts in the Automated Design Process of Digital Circuits. | Wolfgang Ecker, Lothar Schrader |
| 2004 | FDL | SystemVerilog: Interface Based Design. | Peter Jensen, Wolfgang Ecker, Thomas Kruse, Martin Zambaldi |
| 2004 | FDL | Extending the RASSP model for Verification. | Martin Zambaldi, Wolfgang Ecker |
| 2004 | FDL | The Formal Simulation Semantics of SystemVerilog. | Martin Zambaldi, Wolfgang Ecker, Thomas Kruse, Wolfgang Mller |
| 2004 | ISORC | Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking. | Wolfgang Ecker, Volkan Esen, Thomas Steininger, Martin Zambaldi |
| 2004 | ITC | How to Bridge the Gap Between Simulationand Test. | Martin Zambaldi, Wolfgang Ecker |
| 2003 | DAC | Re-use-centric architecture for a fully accelerated testbench environment. | Renate Henftling, Andreas Zinn, Matthias Bauer, Martin Zambaldi, Wolfgang Ecker |
| 2003 | DATE | Platform-Based Testbench Generation. | Renate Henftling, Andreas Zinn, Matthias Bauer, Wolfgang Ecker, Martin Zambaldi |
| 1997 | DAC | Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach. | Matthias Bauer, Wolfgang Ecker |
| 1993 | ICCAD | State look ahead technique for cycle optimization of interacting finite state Moore machines. | Wolfgang Ecker, Michael Hofmeister |