Yung-Fa Chou
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
17
Venues
8
Active years
1994–2018
Best venue rank
A*
Where they publish
Papers
17 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | ASPDAC | A channel-sharable built-in self-test scheme for multi-channel DRAMs. | Kuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou |
| 2017 | ASPDAC | Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. | Wei-Hsun Liao, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen, Ding-Ming Kwai, Yung-Fa Chou |
| 2017 | ICCD | DLL-Assisted Clock Synchronization Method for Multi-Die ICs. | Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou |
| 2016 | ITC | A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. | Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou |
| 2013 | ASPDAC | I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs. | Chi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, Chi-Ping Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai |
| 2013 | VTS | A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. | Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
| 2012 | DAC | Small delay testing for TSVs in 3-D ICs. | Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai |
| 2012 | ITC | A built-in self-test scheme for 3D RAMs. | Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
| 2012 | VTS | A SAR ADC missing-decision level detection and removal technique. | Jiun-Lang Huang, X.-L. Huang, Yung-Fa Chou, Ding-Ming Kwai |
| 2011 | ASPDAC | A self-testing and calibration method for embedded successive approximation register ADC. | Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu |
| 2011 | ETS | A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. | Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai |
| 2011 | VTS | A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. | Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
| 2010 | ASPDAC | CAD reference flow for 3D via-last integrated circuits. | Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu |
| 2004 | ASPDAC | SRAM delay fault modeling and test algorithm development. | Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu |
| 2003 | ICCAD | FAME: A Fault-Pattern Based Memory Failure Analysis Framework. | Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu |
| 2003 | ITC | Fault Pattern Oriented Defect Diagnosis for Memories. | Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang |
| 1994 | ISCAS | General Modular Multiplication by Block Multiplication and Table Lookup. | Cheng-Wen Wu, Yung-Fa Chou |