| 2005 | ASPDAC | Low-power domino circuits using NMOS pull-up on off-critical paths. | Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh |
| 2005 | DATE | Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits. | Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee |
| 2005 | IOLTS | Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. | Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra |
| 2005 | VLSID | Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. | Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh |
| 2005 | VTS | Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. | Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh |
| 2004 | IOLTS | Sizing CMOS Circuits for Increased Transient Error Tolerance. | Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh |
| 2003 | ICCAD | Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level. | Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Hsien-Hsin S. Lee |