Yves Mathieu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
6
Active years
2004–2018
Best venue rank
A*
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | DSD | Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. | Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata |
| 2014 | DATE | Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. | Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata |
| 2014 | FPL | Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. | Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez |
| 2013 | ISCA | Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA. | Zouha Cherif, Jean-Luc Danger, Florent Lozach, Yves Mathieu, Lilian Bossuet |
| 2009 | DATE | Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. | Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar |
| 2009 | RSP | Efficient Data Access Management for FPGA-Based Image Processing SoCs. | Zahir Larabi, Yves Mathieu, Stphane Mancini |
| 2005 | CHES | The "Backend Duplication" Method. | Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet |
| 2004 | DATE | CMOS Structures Suitable for Secured Hardware. | Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost |