| 2026 | ISCAS | A Pico-Watt, Supply-Insensitive All-CMOS Voltage Reference, from -30°C to 160°C for Ultra Low Power IoT Applications. | Soham Bhattacharyya, Anubhab Banerjee, Zia Abbas |
| 2026 | ISCAS | PVT Robust LDO with Curvature Compensated BGR over wide Temperature Range -55°C to 170°C. | Juturu Dhanush, Zia Abbas |
| 2026 | ISCAS | A 445pW, 28Hz Gate-Leakage based Relaxation Oscillator. | Dheeraj Gandepalli, Yuvraj Sinh Rathore, Abhishek Pullela, Zia Abbas |
| 2026 | ISCAS | Low Supply, Impedance-Boosted Current Mirror Using Back-Gate in FD-SOI Technology. | Roopesh G. L, Arpan Jain, Soham Bhattacharyya, Ashfakh Huluvallay, Andleeb Zahra, Zia Abbas |
| 2026 | ISCAS | A 0.5V 72-pW Process and Temperature Compensated Voltage Reference. | Vikkram Srinivasan, Damini Chandi Priya A, Ashfakh Huluvallay, Arpan Jain, Abhishek Pullela, Andleeb Zahra, Zia Abbas |
| 2026 | VLSID | PIDArc: Physics-Informed Deaggregated Architecture for Enhanced Aging-Aware Leakage Power Estimation for FinFET Logic Cells. | Mohammad Rehan Akhtar, Zia Abbas |
| 2026 | VLSID | LeakAnalyser: Uncertainty-Aware Analysis of Leakage Power in Digital Circuits Under PVT Variations. | Sarang Kudtarkar, Zia Abbas |
| 2026 | VLSID | Adaptive Control Strategies in DC-DC Converter for Improved Transient Response and Efficiency for High Load Slew and Fast Switching Loops. | Bharadwaj Subramaniam, Zia Abbas |
| 2025 | ISCAS | Zero-shot Learning in Performance Prediction of Digital VLSI Circuits. | Deepthi Amuru, Zia Abbas |
| 2025 | ISCAS | Towards Designing a Unified DNN Architecture for Analog and Mixed-Signal Circuit Characterization. | Deepthi Amuru, Chetan Mittal, Zia Abbas |
| 2025 | ISCAS | C-Arch: Chained Architecture towards Foundation Modeling of CMOS/FinFET Circuit Designs. | Ritwik Basyas Goswami, Mohammad Rehan Akhtar, Andleeb Zahra, Zia Abbas |
| 2025 | ISCAS | A bidirectional frequency detector independent of input transition density for a wide-tuning range applications. | Abhinav Vajrala, Rajesh Mahadev, Santosh Yachareni, Zia Abbas |
| 2025 | VTS | Low-Power Voltage Reference: Review & Progress. | Abhishek Pullela, Ashfakh Huluvallay, Arpan Jain, Zia Abbas, Inhee Lee |
| 2024 | ISCAS | A Single-Point, Auto-Calibration Technique For PTAT/CTAT Resistance Based Current References. | Arpan Jain, Ashfakh Ali, Dheekshith Akula, Abhishek Pullela, Zia Abbas |
| 2024 | ISCAS | MetaCirc: A Meta-learning Approach for Statistical Leakage Estimation Improvement in Digital Circuits. | Nouduru Venkata Raghavendra, Deepthi Amuru, Zia Abbas |
| 2024 | ISCAS | An inductor-less, cost-effective On-chip CMOS VNA for bio-molecule detection. | Bhartipudi Sahishnavi, Samriddhi Agarwal, Shameer Basha Yerragudi, Naveen Dasari, Andleeb Zahra, Prabhakar Bhimalapuram, Syed Azeemuddin, Zia Abbas |
| 2024 | ISCAS | Enhancing ML model accuracy for Digital VLSI circuits using diffusion models: A study on synthetic data generation. | Prasha Srivastava, Pawan Kumar, Zia Abbas |
| 2024 | VLSID | A 0.8-V, 593-pA Trim-free Duty-cycled All CMOS Current Reference for Ultra-Low Power IoT Applications. | Chetan Mittal, Arnab Dey, Anubhab Banerjee, Ashfakh Ali, Zia Abbas |
| 2023 | ISCAS | An 18.5nW, 62.9dB PSRR, Switched-Capacitor Bandgap Voltage Reference using Low Power Clock Generator Circuit for Biomedical Applications. | Samriddhi Agarwal, Shameer Basha Yerragudi, Naveen Dasari, Inhee Lee, Zia Abbas |
| 2023 | ISCAS | A 162nW, 0.845pJ/step Resistance-to-Digital Converter for Miniature Battery-Powered Sensing Systems. | Arnab Dey, Inhee Lee, Ashfakh Ali, Arpan Jain, Abhishek Pullela, Zia Abbas |
| 2023 | ISCAS | A 2.3nW Gate-Leakage Based Sub-Bandgap Voltage Reference with Line Sensitivity of 0.0066%/V from -40°C to 150°C for Low-Power IoT Systems. | Arnab Dey, Bharadwaj Subramaniam, Ashfakh Ali, Bhartipudi Sahishnavi, Abhishek Pullela, Zia Abbas |
| 2023 | ISCAS | A 7 nW, 1 kHz, -40-170°C Relaxation Oscillator with Switch-Leakage Compensation for Low-Power High-Temperature IoT Systems. | Ashfakh Huluvallay, Abhishek Pullela, Ehab A. Hamed, Arpan Jain, Naveen Dasari, Zia Abbas, Inhee Lee |
| 2023 | ISCAS | A 0.5V, pico-watt, 0.06%/V / 0.03%/V low supply sensitive current/voltage reference without using amplifiers and resistors. | Bhartipudi Sahishnavi, Sampath Kumar, Ashfakh Ali, Arnab Dey, Inhee Lee, Zia Abbas |
| 2022 | ISCAS | A 156pW Gate-Leakage Based Voltage/Current Reference for Low-Power IoT Systems. | Abhishek Pullela, Ashfakh Ali, Arpan Jain, Inhee Lee, Zia Abbas |
| 2022 | VLSID | A 180 | Arpan Jain, Abhishek Pullela, Ashfakh Ali, Zia Abbas |
| 2021 | ISCAS | Algorithm Driven Power-Timing Optimization Methodology for CMOS Digital Circuits Considering PVTA Variations. | Hema Sai Kalluru, Prasenjit Saha, Andleeb Zahra, Zia Abbas |
| 2021 | ISCAS | A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Microsystems. | Abhishek Pullela, Ashfakh Ali, Arpan Jain, Adithya Banthi, Zia Abbas |
| 2021 | ISCAS | Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence. | Prasenjit Saha, Salman Ahmed, Hema Sai Kalluru, Zia Abbas |
| 2021 | VLSID | Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence. | Prasenjit Saha, Hema Sai Kalluru, Zia Abbas |
| 2020 | ISCAS | ATM: Approximate Toom-Cook Multiplication for Speech Processing Applications. | Mohammed Salman Ahmed, Deepthi Amuru, Zia Abbas |
| 2020 | ISCAS | An Efficient Gradient Boosting Approach for PVT Aware Estimation of Leakage Power and Propagation Delay in CMOS/FinFET Digital Cells. | Deepthi Amuru, Mohammed Salman Ahmed, Zia Abbas |
| 2020 | ISCAS | 67ppm/°C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications. | Balaji Yadav Battu, Mounika Kelam, Adithya Bathi, Zia Abbas |
| 2020 | ISCAS | Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance. | Balaji Yadav Battu, Mounika Kelam, Koushik De, Zia Abbas |
| 2020 | VLSID | 3.75ppm/ | Mounika Kelam, Balaji Yadav Battu, Zia Abbas |
| 2019 | ICCD | A Memetic Algorithm Based PVT Variation-Aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design. | Mohammed Salman Ahmed, Zia Abbas |
| 2019 | ISCAS | PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit Design. | Prateek Gupta, Shirisha Gourishetty, Harshini Mandadapu, Zia Abbas |
| 2019 | ISCAS | A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications. | Arpan Jain, Ashfakh Ali, Sai Kiran, Zia Abbas |