| 2025 | DAC | Cayman: Custom Accelerator Generation with Control Flow and Data Access Optimization. | Youwei Xiao, Fan Cui, Zizhang Luo, Weijie Peng, Yun Liang |
| 2025 | ICCAD | Clay: High-level ASIP Framework for Flexible Microarchitecture-Aware Instruction Customization. | Weijie Peng, Youwei Xiao, Yuyang Zou, Zizhang Luo, Yun (Eric) Liang |
| 2024 | FPGA | Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis. | Youwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang |
| 2023 | DAC | Rubick: A Synthesis Framework for Spatial Architectures via Dataflow Decomposition. | Zizhang Luo, Liqiang Lu, Size Zheng, Jieming Yin, Jason Cong, Jianwei Yin, Yun Liang |
| 2023 | FPL | Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAs. | Zizhang Luo, Liqiang Lu, Yicheng Jin, Liancheng Jia, Yun Liang |
| 2021 | DAC | TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra. | Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang |
| 2021 | ISCA | TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. | Liqiang Lu, Naiqing Guan, Yuyue Wang, Liancheng Jia, Zizhang Luo, Jieming Yin, Jason Cong, Yun Liang |
| 2021 | MICRO | Sanger: A Co-Design Framework for Enabling Sparse Attention using Reconfigurable Architecture. | Liqiang Lu, Yicheng Jin, Hangrui Bi, Zizhang Luo, Peng Li, Tao Wang, Yun Liang |
| 2020 | SIGCSE | Teaching Platform for Network Communication and Protocols Using a Micro: bit Based Wheeled Robot. | Zizhang Luo, Yuxuan Zhou, Bohan Yu, Junfeng Hu |