| 2008 | Automatic re-coding of reference code into structured and analyzable SoC models. | Pramod Chandraiah, Rainer Dmer |
| 2008 | Interconnect modeling for improved system-level design optimization. | Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma |
| 2008 | Exploring power management in multi-core systems. | Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer |
| 2008 | ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration. | Giovanni Beltrame, Cristiana Bolchini, Luca Fossati, Antonio Miele, Donatella Sciuto |
| 2008 | Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information. | Alexandros Bartzas, Miguel Pen-Quirs, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias |
| 2008 | Reliability-aware design for nanometer-scale devices. | David Atienza, Giovanni De Micheli, Luca Benini, Jos L. Ayala, Pablo Garca Del Valle, Michael DeBole, Vijaykrishnan Narayanan |
| 2008 | VEBoC: Variation and error-aware design for billions of devices on a chip. | Shoaib Akram, Scott Cromar, Gregory Lucas, Alexandros Papakonstantinou, Deming Chen |
| 2007 | Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. | Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang |
| 2007 | An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization. | Haikun Zhu, Yi Zhu, Chung-Kuan Cheng, David M. Harris |
| 2007 | Approaching Speed-of-light Distortionless Communication for On-chip Interconnect. | Haikun Zhu, Rui Shi, Chung-Kuan Cheng, Hongyu Chen |
| 2007 | A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects. | Nancy Ying Zhou, Zhuo Li, Yuxin Tian, Weiping Shi, Frank Liu |
| 2007 | Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid. | Yu Zhong, Martin D. F. Wong |
| 2007 | Fast Placement Optimization of Power Supply Pads. | Yu Zhong, Martin D. F. Wong |
| 2007 | Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores. | Dan Zhao, Unni Chandran, Hideo Fujiwara |
| 2007 | Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. | Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz |
| 2007 | WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design. | Peng Zhang, Wai-Shing Luk, Yu Song, Jiarong Tong, Pushan Tang, Xuan Zeng |
| 2007 | Challenges to Accuracy for the Design of Deep-Submicron RF-CMOS Circuits. | S. Yoshitomi |
| 2007 | Communication Architecture Synthesis of Cascaded Bus Matrix. | Jun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Choi |
| 2007 | System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production. | Wai-Yeung Yip, Scott Best, Wendemagegnehu T. Beyene, Ralf Schmitt |
| 2007 | Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form. | Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy |
| 2007 | A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks. | Tan Yan, Shuting Li, Yasuhiro Takashima, Hiroshi Murata |
| 2007 | Automating Logic Rectification by Approximate SPFDs. | Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton |
| 2007 | An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools. | Fu-Ching Yang, Ing-Jer Huang |
| 2007 | A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost. | Tsung-Yi Wu, Jr-Luen Tzeng, Kuang-Yao Chen |
| 2007 | A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction. | Pei-Ci Wu, Jhih-Rong Gao, Ting-Chi Wang |