| 2007 | Protocol Transducer Synthesis using Divide and Conquer approach. | Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita |
| 2007 | A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. | Minoru Watanabe, Fuminori Kobayashi |
| 2007 | A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates. | Xiren Wang, Wenjian Yu, Zeyi Wang |
| 2007 | A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture. | Seongmoon Wang, Wenlong Wei |
| 2007 | Symbolic Model Checking of Analog/Mixed-Signal Circuits. | David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda |
| 2007 | FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. | Natarajan Viswanathan, Min Pan, Chris C. N. Chu |
| 2007 | Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. | Ajay Kumar Verma, Paolo Ienne |
| 2007 | DFM reality in sub-nanometer IC design. | N. Verghese, P. Hurat |
| 2007 | Overview on Low Power SoC Design Technology. | Kimiyoshi Usami |
| 2007 | Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations. | Jun Tao, Xuan Zeng, Wei Cai, Yangfeng Su, Dian Zhou, Charles C. Chiang |
| 2007 | A 90nm 816 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. | Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2007 | Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms. | Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod |
| 2007 | Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process. | Subarna Sinha, Jianfeng Luo, Charles C. Chiang |
| 2007 | Xbox360 | David W. Siljenberg, Steve Baumgartner, Tim Buchholtz, Mark Maxson, Trevor Timpane, Jeff Johnson |
| 2007 | Control-Flow Aware Communication and Conflict Analysis of Parallel Processes. | Axel Siebenborn, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel |
| 2007 | A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. | Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2007 | Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. | Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi |
| 2007 | A Graph Reduction Approach to Symbolic Circuit Analysis. | Guoyong Shi, Weiwei Chen, Chuanjin Richard Shi |
| 2007 | A Run-Time Memory Protection Methodology. | Udaya Seshua, Nagaraju Bussa, Bart Vermeulen |
| 2007 | A Multi-Drop Transmission-Line Interconnect in Si LSI. | Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu |
| 2007 | Abstract, Multifaceted Modeling of Embedded Processors for System Level Design. | Gunar Schirner, Andreas Gerstlauer, Rainer Dmer |
| 2007 | A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18m CMOS. | Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Masao Hotta |
| 2007 | Meeting with the Forthcoming IC Design "The Era of Power, Variability and NRE Explosion and a Bit of the Future". | Takayasu Sakurai |
| 2007 | Trace Compaction using SAT-based Reachability Analysis. | Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian |
| 2007 | Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains. | Rob A. Rutenbar |