| 2006 | SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices. | Jitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan |
| 2006 | Diagonal routing in high performance microprocessor design. | Noriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita, Hiroshi Ikeda, Hiroyuki Sugiyama, Hiroaki Komatsu, Yoshiyasu Tanamura, Akihiro Yoshitake, Kazuhiro Nonomura, Kinya Ishizaka, Hiroaki Adachi, Yutaka Mori, Yutaka Isoda, Yaroku Sugiyama |
| 2006 | Delay defect screening for a 2.16GHz SPARC64 microprocessor. | Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi |
| 2006 | Challenging device innovation. | Satoru Ito |
| 2006 | High-throughput decoder for low-density parity-check code. | Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto |
| 2006 | A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression. | Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai |
| 2006 | Open access overview "industrial experience". | Yoshio Inoue |
| 2006 | Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise. | Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga |
| 2006 | Timing-driven placement based on monotone cell ordering constraints. | Chanseok Hwang, Massoud Pedram |
| 2006 | Conversion of reference C code to dataflow model: H.264 encoder case study. | Hyeyoung Hwang, Taewook Oh, Hyunuk Jung, Soonhoi Ha |
| 2006 | Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications. | Qubo Hu, Arnout Vandecappelle, Martin Palkovic, Per Gunnar Kjeldsberg, Erik Brockmeyer, Francky Catthoor |
| 2006 | A routability constrained scan chain ordering technique for test power reduction. | Xuan-Lun Huang, Jiun-Lang Huang |
| 2006 | Fast multi-domain clock skew scheduling for peak current reduction. | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh |
| 2006 | Switching-activity driven gate sizing and Vth assignment for low power design. | Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang |
| 2006 | Spec-based flip-flop and latch repeater planning. | Man Chung Hon |
| 2006 | Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
| 2006 | Functional modeling techniques for efficient SW code generation of video codec applications. | Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya |
| 2006 | TAPHS: thermal-aware unified physical-level and high-level synthesis. | Zhenyu (Peter) Gu, Yonghong Yang, Jia Wang, Robert P. Dick, Li Shang |
| 2006 | Process-induced skew reduction in nominal zero-skew clock trees. | Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown |
| 2006 | Physical design implementation of segmented buses to reduce communication energy. | Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor |
| 2006 | An introduction to OpenAccess: an open source data model and API for IC design. | Michaela Guiney, Eric Leavitt |
| 2006 | A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodels. | Prashant Goyal, Xiaolue Lai, Jaijeet S. Roychowdhury |
| 2006 | Designing a custom architecture for DCT using NISC technology. | Bita Gorjiara, Mehrdad Reshadi, Daniel D. Gajski |
| 2006 | Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. | Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy |
| 2006 | A dynamic test compaction procedure for high-quality path delay testing. | Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato |