| 2025 | A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor. | Yuxuan Pan, Dongzhu Li, Mototsugu Hamada, Atsutake Kosuge |
| 2025 | SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization. | Yikang Ouyang, Yuchao Wu, Dongsheng Zuo, Subhendu Roy, Tinghuan Chen, Zhiyao Xie, Yuzhe Ma |
| 2025 | Large-Scale AGV Routing Based on Multi-FPGA SQA Acceleration. | Thinh NguyenQuang, Kosuke Matsuyama, Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masayuki Ohzeki |
| 2025 | Learning Gate-level Netlist Testability in the Presence of Unknowns through Graph Neural Networks. | Thai-Hoang Nguyen, Youngjin Ju, Dongsub Yoon, Hyojin Choi |
| 2025 | HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads. | Shubham Negi, Utkarsh Saxena, Deepika Sharma, Kaushik Roy |
| 2025 | Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic Operation. | Dondee Navarro, Shin Taniguchi, Chika Tanaka, Kazutoshi Kobayashi, Takashi Sato, Michihiro Shintani |
| 2025 | Through Fabric: A Cross-world Thermal Covert Channel on TEE-enhanced FPGA-MPSoC Systems. | Hassan Nassar, Jeferson Gonzlez-Gmez, Varun Manjunath, Lars Bauer, Jrg Henkel |
| 2025 | High-Effort Logic Synthesis Using Randomized Transduction. | Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Dino Ruic, Xiaoqing Xu |
| 2025 | CACTI-CNFET: an Analytical Tool for Timing, Power, and Area of SRAMs with Carbon Nanotube Field Effect Transistors. | Shinobu Miwa, Eiichiro Sekikawa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda |
| 2025 | Re-Consideration of Correlation Between Interface States and Bulk Traps Using Cryogenic Measurement. | Yuichiro Mitani, Tatsuya Suzuki, Yohei Miyaki |
| 2025 | Transformer Hetero-CiM: Heterogeneous Integration of ReRAM CiM and SRAM CiM for Vision Transformer at Edge Devices. | Naoko Misawa, Tao Wang, Chihiro Matsui, Ken Takeuchi |
| 2025 | Cryo-CMOS Analog Circuits for Spin Qubit Control. | Takuji Miki |
| 2025 | Ultra Low-power Capacitively-coupled Chopper Amplifier Focusing on the Sparsity of Compressed Sensing for EEG Recording. | Kenji Mii, Daisuke Kanemoto, Tetsuya Hirose |
| 2025 | Low quiescent current LDO with FBPEC to improve PSRR specific frequency band for wearable EEG recording devices. | Kenji Mii, Daisuke Kanemoto, Tetsuya Hirose |
| 2025 | Towards Functional Safety of Neural Network Hardware Accelerators: Concurrent Out-of-Distribution Detection in Hardware Using Power Side-Channel Analysis. | Vincent Meyers, Michael Hefenbrock, Mahboobe Sadeghipourrudsari, Dennis Gnad, Mehdi B. Tahoori |
| 2025 | Skip2-LoRA: A Lightweight On-device DNN Fine-tuning Method for Low-cost Edge Devices. | Hiroki Matsutani, Masaaki Kondo, Kazuki Sunaga, Radu Marculescu |
| 2025 | Efficient Arbitrary Precision Acceleration for Large Language Models on GPU Tensor Cores. | Shaobo Ma, Chao Fang, Haikuo Shao, Zhongfeng Wang |
| 2025 | The Unlikely Hero: Nonidealities in Analog Photonic Neural Networks as Built-in Adversarial Defenders. | Haotian Lu, Ziang Yin, Partho Bhoumik, Sanmitra Banerjee, Krishnendu Chakrabarty, Jiaqi Gu |
| 2025 | Rethinking B-epsilon tree Indexing Structure over NVM with the Support of Multi-write Modes. | Hui-Tang Luo, Tseng-Yi Chen |
| 2025 | K-Gate Lock: Multi-Key Logic Locking Using Input Encoding Against Oracle-Guided Attacks. | Kevin Lopez, Amin Rezaei |
| 2025 | Balancing Objective Optimization and Constraint Satisfaction for Robust Analog Circuit Optimization. | Jintao Li, Haochang Zhi, Jiang Xiao, Yanhan Zeng, Weiwei Shan, Yun Li |
| 2025 | HDCC: A Hierarchical Dataflow-Oriented CGRA Compiler for Complex Applications. | Shangli Li, Mingjie Xing, Yanjun Wu |
| 2025 | A Buffer Reservation Scheduling Strategy for Enhancing Performance of NoC Router Bypassing. | Zixuan Liu, Yaoyao Ye |
| 2025 | Exploiting Differential-Based Data Encoding for Enhanced Query Efficiency. | Fangxin Liu, Zongwu Wang, Peng Xu, Shiyuan Huang, Li Jiang |
| 2025 | Processing-Near-Memory with Chip Level 3D-IC. | Miao Liu, Qingqing Sun, David Wei Zhang |