| 2004 | Efficient computation of canonical form for Boolean matching in large libraries. | Debatosh Debnath, Tsutomu Sasao |
| 2004 | Model checking on state transition diagram. | Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay |
| 2004 | An efficient design of non-linear | Sukanta Das, Debdas Dey, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri |
| 2004 | Application of UML for hardware design based on design process model. | Robertas Damasevicius, Vytautas Stuikys |
| 2004 | Verification of timed circuits with symbolic delays. | Robert Claris, Jordi Cortadella |
| 2004 | A dual-band switching digital controller for a buck converter. | Martin Yeung-Kei Chui, Wing-Hung Ki, Chi-Ying Tsui |
| 2004 | NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO. | Min Chu, David J. Allstot, Jeffrey M. Huard, Kim Y. Wong |
| 2004 | Memory access driven storage assignment for variables in embedded system design. | Yoonseo Choi, Taewhan Kim |
| 2004 | Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. | Yiran Chen, Kaushik Roy, Cheng-Kok Koh |
| 2004 | A buffer planning algorithm with congestion optimization. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2004 | Modeling of coplanar waveguide for buffered clock tree. | Jun Chen, Lei He |
| 2004 | A fast congestion estimator for routing with bounded detours. | Lerong Cheng, Xiaoyu Song, Guowu Yang, Zhiwei Tang |
| 2004 | Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. | Yi-Hui Cheng, Yao-Wen Chang |
| 2004 | Optimal planning for mesh-based power distribution. | Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang |
| 2004 | Register binding and port assignment for multiplexer optimization. | Deming Chen, Jason Cong |
| 2004 | Resource-constrained low-power bus encoding with crosstalk delay elimination. | Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim |
| 2004 | Open architecture test system: not why but when! | Srimat T. Chakradhar |
| 2004 | An approach for reducing dynamic power consumption in synchronous sequential digital designs. | Noureddine Chabini, Wayne H. Wolf |
| 2004 | A novel memory size model for variable-mapping in system level design. | Lukai Cai, Haobo Yu, Daniel Gajski |
| 2004 | Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model. | Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya |
| 2004 | Hierarchical extraction and verification of symmetry constraints for analog layout automation. | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, Chuanjin Richard Shi |
| 2004 | LPRAM: a low power DRAM with testability. | Subhasis Bhattacharjee, Dhiraj K. Pradhan |
| 2004 | Exploiting program execution phases to trade power and performance for media workload. | Subhasis Banerjee, G. Surendra, S. K. Nandy |
| 2004 | Golay and wavelet error control codes in VLSI. | Arunkumar Balasundaram, Angelo Pereira, Jun-Cheol Park, Vincent John Mooney III |
| 2004 | Interconnect capacitance estimation for FPGAs. | Jason Helge Anderson, Farid N. Najm |