| 2004 | ShatterPB: symmetry-breaking for pseudo-Boolean formulas. | Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah |
| 2004 | A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. | Kanak Agarwal, Dennis Sylvester, David T. Blaauw |
| 2004 | On deriving equivalent architecture model from system specification. | Samar Abdi, Daniel Gajski |
| 2004 | Gate delay calculation considering the crosstalk capacitances. | Soroush Abbaspour, Massoud Pedram |
| 2004 | Instruction buffering exploration for low energy VLIWs with instruction clusters. | Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal |
| 2003 | An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost. | Changwen Zhuang, Keishi Sakanushi, Liyan Jin, Yoji Kajitani |
| 2003 | A metric for analyzing effective on-chip inductive coupling. | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy |
| 2003 | Energy minimization of real-time tasks on variable voltage processors with transition energy overhead. | Yumin Zhang, Xiaobo Sharon Hu, Danny Z. Chen |
| 2003 | Efficient loop-back testing of on-chip ADCs and DACs. | Hak-soo Yu, Jacob A. Abraham, Sungbae Hwang, Jeongjin Roh |
| 2003 | MAPLE chip: a processing element for a static scheduling centric multiprocessor. | Kenta Yasufuku, Riku Ogawa, Keisuke Iwai, Hideharu Amano |
| 2003 | A low power CMOS circuit with Variable Souce Scheme (VSCMOS). | Takeo Yasuda, Kohji Hosokawa |
| 2003 | Improving boundary element methods for parasitic extraction. | Shu Yan, Jianguo Liu, Weiping Shi |
| 2003 | A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design. | Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu |
| 2003 | Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulation. | Xinyu Wu, Zaiman Chen, Jinmei Lai, Qianling Zhang, Omar Wing, Junyan Ren |
| 2003 | Fast buffer planning and congestion optimization in interconnect-driven floorplanning. | Keith W. C. Wong, Evangeline F. Y. Young |
| 2003 | An on-line approach for power minimization in QoS sensitive systems. | Jennifer L. Wong, Gang Qu, Miodrag Potkonjak |
| 2003 | A 500-MHz low-power five-port CMOS register file. | Jiajing Wang, Qianling Zhang |
| 2003 | An automatic interconnection rectification technique for SoC design integration. | Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou |
| 2003 | Power minimization by clock root gating. | Qi Wang, Sumit Roy |
| 2003 | Register aware scheduling for distributed cache clustered architecture. | Zhong Wang, Xiaobo Sharon Hu, Edwin Hsing-Mean Sha |
| 2003 | Recent developments in ESD protection for RF ICs. | Albert Wang |
| 2003 | Gate-level simulation of quantum circuits. | George F. Viamontes, Manoj Rajagopalan, Igor L. Markov, John P. Hayes |
| 2003 | Data partitioning for maximal scratchpad usage. | Manish Verma, Stefan Steinke, Peter Marwedel |
| 2003 | Logic verification based on diagnosis techniques. | Andreas G. Veneris, Alexander Smith, Magdy S. Abadir |
| 2003 | Design methodology of low-power CMOS RF-ICs. | Tsuneo Tsukahara, Mitsuru Harada, Mamoru Ugajin, Junichi Kodate, Akihiro Yamagishi |