| 2003 | Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designs. | Anurag Tiwari, Karen A. Tomko |
| 2003 | A simulated annealing approach with sequence-pair encoding using a penalty function for the placement problem with boundary constraints. | Satoshi Tayu |
| 2003 | Efficient DDD-based term generation algorithm for analog circuit behavioral modeling. | Sheldon X.-D. Tan, Chuanjin Richard Shi |
| 2003 | Behavioral modeling of EM devices by selective orthogonal matrix least-squares method. | Yuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai |
| 2003 | A hardware/software partitioning algorithm for SIMD processor cores. | Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2003 | Performance-driven multi-level clustering for combinational circuits. | Chin Ngai Sze, Ting-Chi Wang |
| 2003 | A novel LCD driver testing technique using logic test channels. | Chauchin Su, Wei-Juo Wang, Chih-Hu Wang, I. S. Tseng |
| 2003 | Design of a scalable RSA and ECC crypto-processor. | Ming-Cheng Sun, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu |
| 2003 | A highly efficient AES cipher chip. | Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu |
| 2003 | Minimizing total power by simultaneous Vdd/Vth assignment. | Ashish Srivastava, Dennis Sylvester |
| 2003 | Logic foundry: rapid prototyping of FPGA-based DSP systems. | Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima |
| 2003 | Multiple test set generation method for LFSR-based BIST. | Youhua Shi, Zhe Zhang |
| 2003 | A fast and accurate method for interconnect current calculation. | Muzhou Shao, D. F. Wong, Youxin Gao, Huijing Cao, Li-Pen Yuan |
| 2003 | Interconnect-driven floorplanning by searching alternative packings. | Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou |
| 2003 | Applications of adaptive computing systems for signal processing challenges. | Brian Schott, Peter Bellows, Matthew French, Robert Parker |
| 2003 | DFT timing design methodology for at-speed BIST. | Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Masatoshi Kawashima, Kazumi Hatayama, Kazuyuki Nomoto |
| 2003 | Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF. | Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto |
| 2003 | Synthesis of high performance low power PTL circuits. | Debasis Samanta, M. C. Dharmadeep, Ajit Pal |
| 2003 | Finding the best system design flow for a high-speed JPEG encoder. | Kazuo Sakiyama, Patrick Schaumont, Ingrid Verbauwhede |
| 2003 | Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid. | Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura |
| 2003 | Logic optimization for asynchronous speed independent controllers using transduction method. | Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya |
| 2003 | Adaptive wire adjustment for bounded skew Clock Distribution Network. | Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili |
| 2003 | Efficient BIST design for sequential machines using FiF-FoF values in machine states. | Samir Roy, Ujjwal Maulik, Sanghamitra Bandyopadhyay, Subhadip Basu, Biplab Kumar Sikdar |
| 2003 | Adaptive computing: what can it do, where can it go? | Robert Reuss, Jose L. Muoz, Toshiaki Miyazaki, Nader Bagherzadeh, Prith Banerjee, Brad L. Hutchings, Brian Schott |
| 2003 | A new design-for-test technique for reducing SOC test time. | Chakunta Venkata Guru Rao, Dipanwita Roy Chowdhury |