| 2003 | Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies. | Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera |
| 2003 | Run-time energy estimation in system-on-a-chip designs. | Josef Haid, Gerald Kaefer, Christian Steger, Reinhold Weiss |
| 2003 | Routing-aware scan chain ordering. | Puneet Gupta, Andrew B. Kahng, Stefanus Mantik |
| 2003 | Optimal reconfiguration sequence management. | Soheil Ghiasi, Majid Sarrafzadeh |
| 2003 | On effective criterion of path selection for delay testing. | Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka, Shinichi Yosimura |
| 2003 | A still image encoder based on adaptive resolution vector quantization employing needless calculation elimination architecture. | Masanori Fujibayashi, Toshiyuki Nozawa, Takahiro Nakayama, Kenji Mochizuki, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi |
| 2003 | Enhanced symbolic simulation for efficient verification of embedded array systems. | Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Manish Pandey, Magdy S. Abadir |
| 2003 | Event-driven observability enhanced coverage analysis of C programs for functional validation. | Farzan Fallah, Indradeep Ghosh, Masahiro Fujita |
| 2003 | Full-custom vs. standard-cell design flow: an adder case study. | Henrik Eriksson, Per Larsson-Edefors, Tomas Henriksson, Christer Svensson |
| 2003 | A deep submicron power estimation methodology adaptable to variations between power characterization and estimation. | Daniel Eckerbert, Per Larsson-Edefors |
| 2003 | Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL. | Mohamed-Anouar Dziri, Firaz Samet, Flvio Rech Wagner, Wander O. Cesrio, Ahmed Amine Jerraya |
| 2003 | Interactive ray tracing on reconfigurable SIMD MorphoSys. | Haitao Du, Marcos Snchez-lez, Nozar Tabrizi, Nader Bagherzadeh, Manuel Lois Anido, Milagros Fernndez |
| 2003 | Semi-formal test generation and resolving a temporal abstraction problem in practice: industrial application. | Julia Dushina, Mike Benjamin, Daniel Geist |
| 2003 | Towards on-chip fault-tolerant communication. | Tudor Dumitras, Sam Kerner, Radu Marculescu |
| 2003 | Typing abstractions and management in a component framework. | Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta |
| 2003 | VLSI module placement with pre-placed modules and considering congestion using solution space smoothing. | Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu |
| 2003 | Design of a CMOS test chip for package models and I/O characteristics verification. | Chetan Despande, Tom Chen |
| 2003 | Design tools for 3-D integrated circuits. | Shamik Das, Anantha P. Chandrakasan, Rafael Reif |
| 2003 | Silicon virtual prototyping: the new cockpit for nanometer chip design. | Wei-Jin Dai, Dennis Jen-Hsin Huang, Chin-Chih Chang, Michel Courtoy |
| 2003 | Hardware verification using ANSI-C programs as a reference. | Edmund M. Clarke, Daniel Kroening |
| 2003 | The Y-architecture: yet another on-chip interconnect solution. | Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng |
| 2003 | Non-slicing floorplans with boundary constraints using generalized polish expression. | De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang |
| 2003 | Design and implementation of a video-oriented network-interface-card system. | Ming-Chih Chen, Shen-Fu Hsiao, Cheng-Hsien Yang |
| 2003 | Floorplanning with power supply noise avoidance. | Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong |
| 2003 | A buffer planning algorithm based on dead space redistribution. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |