| 1995 | Future direction of synthesizability and interoperability of HDL's: part 1. | Masaharu Imai, Eugenio Villar |
| 1995 | Synthesis of false loop free circuits. | Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang |
| 1995 | Implicit prime compatible generation for minimizing incompletely specified finite state machines. | Hiroyuki Higuchi, Yusuke Matsunaga |
| 1995 | High-level synthesis scheduling and allocation using genetic algorithms. | Marc J. M. Heijligers, L. J. M. Cluitmans, Jochen A. G. Jess |
| 1995 | A datapath synthesis system for the reconfigurable datapath architecture. | Reiner W. Hartenstein, Rainer Kress |
| 1995 | Logic optimization by an improved sequential redundancy addition and removal techniques. | Uwe Glser, Kwang-Ting Cheng |
| 1995 | A hardware-software co-simulator for embedded system design and debugging. | Abhijit Ghosh, Michael Bershteyn, Ross Casley, Chiahon Chien, Ankur Jain, Michael Lipsie, Donald Tarrodaychik, Osamu Yamamo |
| 1995 | A new layout synthesis for leaf cell design. | Masahiro Fukui, Noriko Shinomiya, Toshiro Akino |
| 1995 | EMPAR: an interactive synthesis environment for hardware emulations. | Wen-Jong Fang, Allen C.-H. Wu, Tsing-Gen Lee |
| 1995 | Assessing the feasibility of interface designs before their implementation. | Marco A. Escalante, Nikitas J. Dimopoulos |
| 1995 | Learning heuristics by genetic algorithms. | Rolf Drechsler, Bernd Becker |
| 1995 | Current and charge estimation in CMOS circuits. | Sanjay Dhar, Dave J. Gurney |
| 1995 | A new and accurate interconnection delay time evaluation in a general tree-type network. | Denis Deschacht, Christophe Dabrin |
| 1995 | GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions. | Debatosh Debnath, Tsutomu Sasao |
| 1995 | A built-in self test scheme for VLSI. | T. Raju Damarla, Wei Su, Gerald T. Michael, Moon J. Chung, Charles E. Stroud |
| 1995 | Exploitation signal flow and logic dependency in standard cell placement. | Jason Cong, Dongmin Xu |
| 1995 | A hardware-oriented design for weighted median filters. | Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao |
| 1995 | Flexible optimization of fixed polarity Reed-Muller expansions for multiple and output completely and incompletely specified boolean functions. | Chip-Hong Chang, Bogdan J. Falkowski |
| 1995 | Stoht: an SDL-to-hardware translator. | Ivanil S. Bonatti, Renato J. O. Figueiredo |
| 1995 | BIST with negligible aliasing through random cover circuits. | T. Bogue, Helmut Jrgensen, Michael Gssel |
| 1995 | A hardware/software codesign method for pipelined instruction set processor using adaptive database. | Nguyen-Ngoc Bnh, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi |
| 1995 | A tool for measuring quality of test pattern for LSIs' functional design. | Takashi Aoki, Tomoji Toriyama, Kenji Ishikawa, Kennosuke Fukami |
| 1995 | Fanout-tree restructuring algorithm for post-placement timing optimization. | T. Aoki, Masami Murakata, Takashi Mitsuhashi, Nobuyuki Goto |