| 1995 | Limits of using signatures for permutation independent Boolean comparison. | Janett Mohnke, Paul Molitor, Sharad Malik |
| 1995 | Extending pitchmaking algorithms to layouts with multiple grid constraints. | Hiroshi Miyashita |
| 1995 | An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctutation. | Mikako Miyama, Goichi Yokomizo, Masato Iwabuchi, Masami Kinoshita |
| 1995 | Techniques for low power realization for FIR filters. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1995 | Search space reduction in high level synthesis by use of an initial circuit. | Atsushi Masuda, Hiroshi Imai, Jeffery P. Hansen, Masatoshi Sekine |
| 1995 | Power recduction by gate sizing with path-oriented slack calculation. | How-Rern Lin, TingTing Hwang |
| 1995 | Improved computational methods and lazy evaluation of the Ordered Ternary Decision Diagram. | Per Lindgren |
| 1995 | Logic rectification and synthesis for engineering change. | Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen |
| 1995 | A CSIC implementation with POCSAG decoder and microcontroller for paging applications. | Jaeyoung Lim, Geon Kim, I.-S. O, Joonghwee Cho, Youngjin Kim, Hoyoung Kim |
| 1995 | Technology mapping for FPGAs with complex block architectures by fuzzy logic techniques. | Jung-Yong Lee, Eugene Shragowitz |
| 1995 | Architectural simulation for a programmable DSP chip set. | Jong Tae Lee, Jaemin Kim, Jae Cheol Son |
| 1995 | A scheduling algorithm for multiport memory minimization in datapath synthesis. | Hae-Dong Lee, Sun-Young Hwang |
| 1995 | Automatic design for bit-serial MSPA architecture. | Hiroaki Kunieda, Yusong Liao, Dongju Li, Kazuhito Ito |
| 1995 | On hazard-free implementation of speed-independent circuits. | Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev |
| 1995 | A model-adaptable MOSFET parameter extraction system. | Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru |
| 1995 | A new performance driven placement method with the Elmore delay model for row based VLSIs. | Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru |
| 1995 | Delay abstraction in combinational logic circuits. | Noriya Kobayashi, Sharad Malik |
| 1995 | Performance-driven circuit partitioning for prototyping by using multiple FPGA chips. | Chunghee Kim, Hyunchul Shin, Young-Uk Yu |
| 1995 | An integrated hardware-software cosimulation environment for heterogeneous systems prototyping. | Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha |
| 1995 | A new system partitioning method under performance and physical constraints for multi-chip modules. | Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida |
| 1995 | Generic fuzzy logic CAD development tool. | Eric Q. Kang, Eugene Shragowitz |
| 1995 | EDIF version 350/400 and information modeling. | Hilary J. Kahn |
| 1995 | Integrated interconnect circuit modeling for VLSI design. | Won-Young Jung, Ghun-Up Cha, Young-Bae Kim, Jun-Ho Baek, Choon-Kyung Kim |
| 1995 | Reclocking for high-level synthesis. | Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran |
| 1995 | Manipulation of regular expressions under length constraints using zero-suppressed-BDDs. | Shinya Ishihara, Shin-ichi Minato |