| 2022 | Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. | Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz |
| 2022 | A Versatile Mapping Approach for Technology Mapping and Graph Optimization. | Alessandro Tempia Calvino, Heinz Riener, Shubham Rai, Akash Kumar, Giovanni De Micheli |
| 2022 | Limiting the Search Space in Optimal Quantum Circuit Mapping. | Lukas Burgholzer, Sarah Schneider, Robert Wille |
| 2022 | Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper). | Ahmet Faruk Budak, Zixuan Jiang, Keren Zhu, Azalia Mirhoseini, Anna Goldie, David Z. Pan |
| 2022 | Delay Optimization of Combinational Logic by AND-OR Path Restructuring. | Ulrich Brenner, Anna Silvanus |
| 2022 | CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams. | Rami Beidas, Jason Helge Anderson |
| 2022 | Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. | Xiqiong Bai, Ziran Zhu, Peng Zou, Jianli Chen, Jun Yu, Yao-Wen Chang |
| 2022 | Computation-in-Memory Accelerators for Secure Graph Database: Opportunities and Challenges. | Md Tanvir Arafin |
| 2022 | Design Close to the Edge for Advanced Technology using Machine Learning and Brain-Inspired Algorithms. | Hussam Amrouch, Florian Klemme, Paul R. Genssler |
| 2022 | FirVer: Concolic Testing for Systematic Validation of Firmware Binaries. | Tashfia Alam, Zhenkun Yang, Bo Chen, Nicholas Armour, Sandip Ray |
| 2022 | A Fast and Accurate Middle End of Line Parasitic Capacitance Extraction for MOSFET and FinFET Technologies Using Machine Learning. | Mohamed Saleh Abouelyazid, Sherif Hammouda, Yehea Ismail |
| 2022 | SPRoute 2.0: A detailed-routability-driven deterministic parallel global router with soft capacity. | Jiayuan He, Udit Agarwal, Yihang Yang, Rajit Manohar, Keshav Pingali |
| 2022 | XCelHD: An Efficient GPU-Powered Hyperdimensional Computing with Parallelized Training. | Jaeyoung Kang, Behnam Khaleghi, Yeseong Kim, Tajana Rosing |
| 2022 | EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper). | Jiaxi Zhang, Qiuyang Gao, Yijiang Guo, Bizhao Shi, Guojie Luo |
| 2022 | Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. | Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan |
| 2022 | Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper). | Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan |
| 2021 | PCBench: Benchmarking of Board-Level Hardware Attacks and Trojans. | Huifeng Zhu, Xiaolong Guo, Yier Jin, Xuan Zhang |
| 2021 | Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse Scheme. | Shuxin Zhou, Huandong Wang, Dong Tong |
| 2021 | DP-Sim: A Full-stack Simulation Infrastructure for Digital Processing In-Memory Architectures. | Minxuan Zhou, Mohsen Imani, Yeseong Kim, Saransh Gupta, Tajana Rosing |
| 2021 | SAC: A Stream Aware Write Cache Scheme for Multi-Streamed Solid State Drives. | Bo Zhou, Chuanming Ding, Yina Lv, Chun Jason Xue, Qingfeng Zhuge, Edwin H.-M. Sha, Liang Shi |
| 2021 | Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment. | Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young |
| 2021 | Light: A Scalable and Efficient Wavelength-Routed Optical Networks-On-Chip Topology. | Zhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann |
| 2021 | 1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method. | Li-Cheng Zheng, Hao-Ju Chang, Yung-Chih Chen, Jing-Yang Jou |
| 2021 | A Quantized Training Framework for Robust and Accurate ReRAM-based Neural Network Accelerators. | Chenguang Zhang, Pingqiang Zhou |
| 2021 | 28GHz Phase Shifter with Temperature Compensation for 5G NR Phased-array Transceiver. | Yi Zhang, Jian Pang, Kiyoshi Yanagizawa, Atsushi Shirane, Kenichi Okada |