| 2019 | Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators. | Jiajun Li, Ying Wang, Bosheng Liu, Yinhe Han, Xiaowei Li |
| 2019 | Fault tolerance in neuromorphic computing systems. | Mengyun Liu, Lixue Xia, Yu Wang, Krishnendu Chakrabarty |
| 2019 | A system-level perspective to understand the vulnerability of deep learning systems. | Tao Liu, Nuo Xu, Qi Liu, Yanzhi Wang, Wujie Wen |
| 2019 | Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators. | Bosheng Liu, Xiaoming Chen, Ying Wang, Yinhe Han, Jiajun Li, Haobo Xu, Xiaowei Li |
| 2019 | MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs. | Yen-Chun Liu, Tung-Chieh Chen, Yao-Wen Chang, Sy-Yen Kuo |
| 2019 | Integrated flow for reverse engineering of nanoscale technologies. | Bernhard Lippmann, Michael Werner, Niklas Unverricht, Aayush Singla, Peter Egger, Anja Dbotzky, Horst A. Gieser, Martin Rasche, Oliver Kellermann, Helmut Graeb |
| 2019 | Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator. | Jilan Lin, Zhenhua Zhu, Yu Wang, Yuan Xie |
| 2019 | Redeeming chip-level power efficiency by collaborative management of the computation and communication. | Ning Lin, Hang Lu, Xin Wei, Xiaowei Li |
| 2019 | Autonomous vehicle routing in multiple intersections. | Sheng-Hao Lin, Tsung-Yi Ho |
| 2019 | Routing in optical network-on-chip: minimizing contention with guaranteed thermal reliability. | Mengquan Li, Weichen Liu, Lei Yang, Peng Chen, Duo Liu, Nan Guan |
| 2019 | Execution of provably secure assays on MEDA biochips to thwart attacks. | Tung-Che Liang, Mohammed Shayan, Krishnendu Chakrabarty, Ramesh Karri |
| 2019 | Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array biochips. | Tung-Che Liang, Yun-Sheng Chan, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee |
| 2019 | Design of gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS. | Atsuki Kobayashi, Yuya Nishio, Kenya Hayashi, Shigeki Arata, Kiichi Niitsu |
| 2019 | Low standby power CMOS delay flip-flop with data retention capability. | Nobuaki Kobayashi, Tadayoshi Enomoto |
| 2019 | Development of a high stability, low standby power six-transistor CMOS SRAM employing a single power supply. | Nobuaki Kobayashi, Tadayoshi Enomoto |
| 2019 | SeRoHAL: generation of selectively robust hardware abstraction layers for efficient protection of mixed-criticality systems. | Petra R. Kleeberger, Juana Rivera, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2019 | On-chip memory optimization for high-level synthesis of multi-dimensional data on FPGA. | Daewoo Kim, Sugil Lee, Jongeun Lee |
| 2019 | In-memory batch-normalization for resistive memory based binary neural network hardware. | Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim |
| 2019 | A fast machine learning-based mask printability predictor for OPC acceleration. | Bentian Jiang, Hang Zhang, Jinglei Yang, Evangeline F. Y. Young |
| 2019 | HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing. | Houxiang Ji, Li Jiang, Tianjian Li, Naifeng Jing, Jing Ke, Xiaoyao Liang |
| 2019 | Quantum circuit compilers using gate commutation rules. | Toshinari Itoko, Rudy Raymond, Takashi Imamichi, Atsushi Matsuo, Andrew W. Cross |
| 2019 | FACH: FPGA-based acceleration of hyperdimensional computing by reducing computational complexity. | Mohsen Imani, Sahand Salamat, Saransh Gupta, Jiani Huang, Tajana Rosing |
| 2019 | Multi-angle bended heat pipe design using x-architecture routing with dynamic thermal weight on mobile devices. | Hsuan-Hsuan Hsiao, Hong-Wen Chiou, Yu-Min Lee |
| 2019 | A figure of merit for assertions in verification. | Samuel Hertz, Debjit Pal, Spencer Offenberger, Shobha Vasudevan |
| 2019 | Maximizing power state cross coverage in firmware-based power management. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |