| 2018 | Multi-level droplet routing in active-matrix based digital-microfluidic biochips. | Guan-Ruei Lu, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen |
| 2018 | A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion. | Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan |
| 2018 | Running sparse and low-precision neural network: When algorithm meets hardware. | Bing Li, Wei Wen, Jiachen Mao, Sicheng Li, Yiran Chen, Hai Helen Li |
| 2018 | Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems. | Xiaoxiao Liu, Wei Wen, Xuehai Qian, Hai Li, Yiran Chen |
| 2018 | A 5.8 GHz DSRC digitally controlled CMOS RF-SoC transceiver for China ETC. | Huimin Liu, Xiongfei Qu, Lingling Cao, Ruifeng Liu, Yuanzhi Zhang, Meijuan Zhang, Xiaoqiang Li, Wenshen Wang, Chao Lu |
| 2018 | Security analysis and enhancement of model compressed deep learning systems under adversarial attacks. | Qi Liu, Tao Liu, Zihao Liu, Yanzhi Wang, Yier Jin, Wujie Wen |
| 2018 | PT-spike: A precise-time-dependent single spike neuromorphic architecture with efficient supervised learning. | Tao Liu, Lei Jiang, Yier Jin, Gang Quan, Wujie Wen |
| 2018 | SCBench: A benchmark design suite for SystemC verification and validation. | Bin Lin, Fei Xie |
| 2018 | Supporting compressed-sparse activations and weights on SIMD-like accelerator for sparse convolutional neural networks. | Chien-Yu Lin, Bo-Cheng Lai |
| 2018 | An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate. | Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi |
| 2018 | Large-scale short-term urban taxi demand forecasting using deep learning. | Siyu Liao, Liutong Zhou, Xuan Di, Bo Yuan, Jinjun Xiong |
| 2018 | A switched-loop-filter PLL with fast phase-error correction technique. | Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi |
| 2018 | BUQS: Battery- and user-aware QoS scaling for interactive mobile devices. | Wooseok Lee, Reena Panda, Dam Sunwoo, Jos A. Joao, Andreas Gerstlauer, Lizy K. John |
| 2018 | Low power FSK transceiver using ADPLL with direct modulation and integrated SPDT for BLE application. | Dong-Soo Lee, Sung-Jin Kim, SeongJin Oh, Gyusub Won, Thi Kim Nga Truong, Imran Ali, Hamed Abbasizadeh, Behnam Samadpoor Rikan, Kang-Yoon Lee |
| 2018 | A 16.6-pJ/b 150-Mb/s body-channel communication transceiver with decision feedback equalization improving >200x area efficiency. | Ji-Hoon Lee, Kwangmin Kim, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim |
| 2018 | A 300-pW audio ΑΣ modulator with 100.5-dB DR using dynamic bias inverter. | Sangwoo Lee, Woojin Jo, Seung-Woo Song, Youngcheol Chae |
| 2018 | FastPass: Fast timing path search for generalized timing exception handling. | Pei-Yu Lee, Iris Hui-Ru Jiang, Tung-Chieh Chen |
| 2018 | An ultra-low-noise differential relaxation oscillator based on a swing-boosting scheme. | Junghyup Lee, Arup K. George, Minkyu Je |
| 2018 | 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface. | Yeonho Lee, Yoonjae Choi, Chulwoo Kim |
| 2018 | A highly compressed timing macro-modeling algorithm for hierarchical and incremental timing analysis. | Tin-Yin Lai, Martin D. F. Wong |
| 2018 | Effect of aging on linear and nonlinear MUX PUFs by statistical modeling. | Anoop Koyily, Satya Venkata Sandeep Avvaru, Chen Zhou, Chris H. Kim, Keshab K. Parhi |
| 2018 | System level performance analysis and optimization for the adaptive clocking based multi-core processor. | Byung-Su Kim, Joon-Sung Yang |
| 2018 | Real-time depth map processor for offset aperture based single camera system. | Hyeji Kim, Jinyeon Lim, Yeongmin Lee, Woojin Yun, Young-Gyu Kim, Wonseok Choi, Asim Khan, Muhammad Umar Karim Khan, Said Homidov, Hyun Sang Park, Chong-Min Kyung |
| 2018 | An optimal gate design for the synthesis of ternary logic circuits. | Sunmean Kim, Taeho Lim, Seokhyeong Kang |
| 2018 | A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop. | Dongin Kim, SeongHwan Cho |