| 2017 | Improving LDPC performance via asymmetric sensing level placement on flash memory. | Qiao Li, Liang Shi, Chun Jason Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha |
| 2017 | Towards acceleration of deep convolutional neural networks using stochastic computing. | Ji Li, Ao Ren, Zhe Li, Caiwen Ding, Bo Yuan, Qinru Qiu, Yanzhi Wang |
| 2017 | Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits. | Jai-Ming Lin, Bo-Heng Yu, Li-Yen Chang |
| 2017 | Scalable frequent-pattern mining on nonvolatile memories. | Yi Lin, Po-Chun Huang, Duo Liu, Liang Liang |
| 2017 | Guiding template-aware routing considering redundant via insertion for directed self-assembly. | Kun-Lin Lin, Shao-Yun Fang |
| 2017 | Processor shield for L1 data cache software-based on-line self-testing. | Ching-Wen Lin, Chung-Ho Chen |
| 2017 | An artificial neural network approach for screening test escapes. | Fan Lin, Kwang-Ting Cheng |
| 2017 | Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits. | Tuotian Liao, Lihong Zhang |
| 2017 | Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. | Wei-Hsun Liao, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen, Ding-Ming Kwai, Yung-Fa Chou |
| 2017 | BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems. | Shiqi Lian, Ying Wang, Yinhe Han, Xiaowei Li |
| 2017 | Yield-driven redundant power bump assignment for power network robustness. | Yu-Min Lee, Chi-Han Lee, Yan-Cheng Zhu |
| 2017 | DLPS: Dynamic laser power scaling for optical Network-on-Chip. | Fan Lan, Rui Wu, Chong Zhang, Yun Pan, Kwang-Ting (Tim) Cheng |
| 2017 | Adaptive load distribution in mixed-critical Networks-on-Chip. | Adam Kostrzewa, Sebastian Tobuschat, Leonardo Ecco, Rolf Ernst |
| 2017 | Design of an energy-autonomous bio-sensing system using a biofuel cell and 0.19V 53μW integrated supply-sensing sensor with a supply-insensitive temperature sensor and inductive-coupling transmitter. | Atsuki Kobayashi, Kei Ikeda, Yudai Ogawa, Matsuhiko Nishizawa, Kazuo Nakazato, Kiichi Niitsu |
| 2017 | A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. | Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo |
| 2017 | Algorithm for synthesis and exploration of clock spines. | Youngchan Kim, Taewhan Kim |
| 2017 | Exact routing for micro-electrode-dot-array digital microfluidic biochips. | Oliver Keszcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler |
| 2017 | Design of multiple fanout clock distribution network for rapid single flux quantum technology. | Naveen Katam, Alireza Shafaei, Massoud Pedram |
| 2017 | MUTARCH: Architectural diversity for FPGA device and IP security. | Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, Swarup Bhunia |
| 2017 | CMOS-on-quartz pulse generator for low power applications. | Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada |
| 2017 | Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. | Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu |
| 2017 | MPIM: Multi-purpose in-memory processing using configurable resistive memory. | Mohsen Imani, Yeseong Kim, Tajana Rosing |
| 2017 | Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface. | Masaharu Imai, Yoshinori Takeuchi, Jun Ohta, Gregg Jrgen Suaning, Chung-Yu Wu, Napoleon Torres-Martinez |
| 2017 | A scalable time-domain biosensor array using logarithmic cyclic time-attenuation-based TDC for high-resolution and large-scale bio-imaging. | Kei Ikeda, Atsuki Kobayashi, Kazuo Nakazato, Kiichi Niitsu |
| 2017 | An image sensor/processor 3D stacked module featuring ThruChip interfaces. | Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura |