| 2016 | Stitch aware detailed placement for multiple e-beam lithography. | Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan |
| 2016 | Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures. | Xinhan Lin, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2016 | Generating high coverage tests for SystemC designs using symbolic execution. | Bin Lin, Zhenkun Yang, Kai Cong, Fei Xie |
| 2016 | Speed binning with high-quality structural patterns from functional timing analysis (FTA). | Louis Y.-Z. Lin, Charles H.-P. Wen |
| 2016 | Recent research development and new challenges in analog layout synthesis. | Mark Po-Hung Lin, Yao-Wen Chang, Chih-Ming Hung |
| 2016 | Cut redistribution with directed self-assembly templates for advanced 1-D gridded layouts. | Zhi-Wen Lin, Yao-Wen Chang |
| 2016 | Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques. | Mingzhong Li, Chio-In Ieong, Man-Kay Law, Pui-In Mak, Mang I Vai, Sio-Hang Pun, Rui Paulo Martins |
| 2016 | Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction. | Shang-Yi Li, Pei-Yuan Chou, Jinn-Shyan Wang |
| 2016 | Logic and memory design using spin-based circuits. | Zhaoxin Liang, Meghna G. Mankalale, Brandon Del Bel, Sachin S. Sapatnekar |
| 2016 | Minimum implant area-aware placement and threshold voltage refinement. | Seong-I Lei, Wai-Kei Mak, Chris Chu |
| 2016 | Chain-based pin count minimization for general-purpose digital microfluidic biochips. | Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang, Jing-Yang Jou |
| 2016 | Hardware Reliability margining for the dark silicon era. | Liangzhen Lai, Puneet Gupta |
| 2016 | Dynamic admission control for real-time networks-on-chips. | Adam Kostrzewa, Selma Saidi, Leonardo Ecco, Rolf Ernst |
| 2016 | An energy-efficient random number generator for stochastic circuits. | Kyounghoon Kim, Jongeun Lee, Kiyoung Choi |
| 2016 | Enabling multi-layer cyber-security assessment of Industrial Control Systems through Hardware-In-The-Loop testbeds. | Anastasis Keliris, Charalambos Konstantinou, Nektarios Georgios Tsoutsos, Raghad Baiad, Michail Maniatakos |
| 2016 | A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. | Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera |
| 2016 | Clock buffer polarity assignment utilizing useful clock skews for power noise reduction. | Deokjin Joo, Taewhan Kim |
| 2016 | Ordered Escape routing for grid pin array based on Min-cost Multi-commodity Flow. | Fengxian Jiao, Sheqin Dong |
| 2016 | Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read. | Lei Jiang, Wujie Wen, Danghui Wang, Lide Duan |
| 2016 | SPARTA: A scheduling policy for thwarting differential power analysis attacks. | Ke Jiang, Petru Eles, Zebo Peng, Sudipta Chattopadhyay, Lejla Batina |
| 2016 | Energy-efficient system design for IoT devices. | Hrishikesh Jayakumar, Arnab Raha, Younghyun Kim, Soubhagya Sutar, Woo Suk Lee, Vijay Raghunathan |
| 2016 | Sub-W QRS detection processor using quadratic spline wavelet transform and maxima modulus pair recognition for power-efficient wireless arrhythmia monitoring. | Chio-In Ieong, Pui-In Mak, Mang I Vai, Rui Paulo Martins |
| 2016 | Electromigration recovery modeling and analysis under time-dependent current and temperature stressing. | Xin Huang, Valeriy Sukharev, Taeyoung Kim, Hai-Bao Chen, Sheldon X.-D. Tan |
| 2016 | Analytical thruchip inductive coupling channel design optimization. | Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda |
| 2016 | Accurate remaining range estimation for Electric vehicles. | Joonki Hong, Sangjun Park, Naehyuck Chang |