| 2013 | High-frequency circuit design for 25 Gb/s4 optical transceiver. | Norio Chujo, Takashi Takemoto, Fumio Yuki, Hiroki Yamashita |
| 2013 | An efficient compression scheme for checkpointing of FPGA-based digital mockups. | Ting-Shuo Chou, Tony Givargis, Chen Huang, Bailey Miller, Frank Vahid |
| 2013 | Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms. | Doris Chen, Deshanand P. Singh |
| 2013 | A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS. | Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto |
| 2013 | Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs. | Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu |
| 2013 | The Liquid Metal IP bridge. | Perry Cheng, Stephen J. Fink, Rodric M. Rabbah, Sunil Shukla |
| 2013 | Optimization of overdrive signoff. | Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath |
| 2013 | A flexible fixed-outline floorplanning methodology for mixed-size modules. | Kai-Chung Chan, Chao-Jam Hsu, Jia-Ming Lin |
| 2013 | A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules. | Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen |
| 2013 | ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noise. | Yuan-Ying Chang, Yoshi Shih-Chieh Huang, Vijaykrishnan Narayanan, Chung-Ta King |
| 2013 | Real-time partitioned scheduling on multi-core systems with local and global memories. | Che-Wei Chang, Jian-Jia Chen, Tei-Wei Kuo, Heiko Falk |
| 2013 | Reevaluating the latency claims of 3D stacked memories. | Daniel W. Chang, Gyungsu Byun, Hoyoung Kim, Minwook Ahn, Soojung Ryu, Nam Sung Kim, Michael J. Schulte |
| 2013 | Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs. | Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, Sung Kyu Lim |
| 2013 | Full exploitation of process variation space for continuous delivery of optimal delay test quality. | Baris Arslan, Alex Orailoglu |
| 2013 | Support tools for porting legacy applications to multicore. | Yuri Ardila, Natsuki Kawai, Takashi Nakamura, Yosuke Tamura |
| 2013 | DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks. | Jude Angelo Ambrose, Hctor Pettenghi, Leonel Sousa |
| 2013 | MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits. | Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2013 | Application-specific fault-tolerant architecture synthesis for digital microfluidic biochips. | Mirela Alistar, Paul Pop, Jan Madsen |
| 2013 | Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches. | Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi |
| 2012 | Fast floating random walk algorithm formulti-dielectric capacitance extraction with numerical characterization of Green's functions. | Hao Zhuang, Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye |
| 2012 | Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems. | Yan Zheng, Peter Lisherness, Saeed Shamshiri, Amirali Ghofrani, Shiyuan Yang, Kwang-Ting Cheng |
| 2012 | Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs. | Xin Zhao, Sung Kyu Lim |
| 2012 | CODA: A concurrent online delay measurement architecture for critical paths. | Yubin Zhang, Haile Yu, Qiang Xu |
| 2012 | Efficient pattern relocation for EUV blank defect mitigation. | Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Rasit Onur Topaloglu |
| 2012 | Relaxed synchronization technique for speeding-up the parallel simulation of multiprocessor systems. | Dukyoung Yun, Sungchan Kim, Soonhoi Ha |