| 2011 | A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. | Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng |
| 2011 | TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler. | Shuo-Hung Chen, Hsiao-Mei Lin, Ching-Chou Hsieh, Chih-Tsun Huang, Jing-Jia Liou, Yeh-Ching Chung |
| 2011 | Emerging sensing techniques for emerging memories. | Yiran Chen, Hai Li |
| 2011 | Future electron-beam lithography and implications on design and CAD tools. | Jack J. H. Chen, Faruk Krecinic, Jen-Hom Chen, Raymond P. S. Chen, Burn J. Lin |
| 2011 | Design and chip implementation of a heterogeneous multi-core DSP. | Shuming Chen, Xiaowen Chen, Yi Xu, Jianghua Wan, Jianzhuang Lu, Xiangyuan Liu, Shenggang Chen |
| 2011 | A physical-location-aware fault redistribution for maximum IR-drop reduction. | Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang |
| 2011 | A fast and effective dynamic trace-based method for analyzing architectural performance. | Yi-Siou Chen, Lih-Yih Chiou, Hsun-Hsiang Chang |
| 2011 | Leakage conscious DVS scheduling for peak temperature minimization. | Vivek Chaturvedi, Gang Quan |
| 2011 | ILP-based inter-die routing for 3D ICs. | Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, Chien-Nan Jimmy Liu |
| 2011 | Cut-demand based routing resource allocation and consolidation for routability enhancement. | Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak |
| 2011 | Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC. | Meng-Fan Chang, Pi-Feng Chiu, Shyh-Shyuan Sheu |
| 2011 | On the design and analysis of fault tolerant NoC architecture using spare routers. | Yung-Chang Chang, Ching-Te Chiu, Shih-Yin Lin, Chung-Kai Liu |
| 2011 | On the impact of gate oxide degradation on SRAM dynamic and static write-ability. | Vikas Chandra, Robert C. Aitken |
| 2011 | Controlling NBTI degradation during static burn-in testing. | Ashutosh Chakraborty, David Z. Pan |
| 2011 | The alarms project: A hardware/software approach to addressing parameter variations. | David M. Brooks |
| 2011 | CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits. | Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, Giovanni De Micheli |
| 2011 | Efficient sensitivity-based capacitance modeling for systematic and random geometric variations. | Yu Bi, Pieter Harpe, N. P. van der Meijs |
| 2011 | Register pressure aware scheduling for high level synthesis. | Rami Beidas, Wai Sum Mong, Jianwen Zhu |
| 2011 | A 4.32 mm | Dan Bao, Chuan Wu, Yan Ying, Yun Chen, Xiaoyang Zeng |
| 2011 | Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. | Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin |
| 2011 | Healthcare of an organization: Using wearable sensors and feedback system for energizing workers. | Koji Ara, Tomoaki Akitomi, Nobuo Sato, Satomi Tsuji, Miki Hayakawa, Yoshihiro Wakisaka, Norio Ohkubo, Rieko Otsuka, Fumiko Beniyama, Norihiko Moriwaki, Kazuo Yano |
| 2011 | Area-efficient FPGA logic elements: Architecture and synthesis. | Jason Helge Anderson, Qiang Wang |
| 2011 | Jitter amplifier for oscillator-based true random number generator. | Takehiko Amaki, Masanori Hashimoto, Takao Onoye |
| 2011 | A polynomial-time custom instruction identification algorithm based on dynamic programming. | Junwhan Ahn, Imyong Lee, Kiyoung Choi |
| 2010 | Constrained global scheduling of streaming applications on MPSoCs. | Jun Zhu, Ingo Sander, Axel Jantsch |