| 2010 | Design time body bias selection for parametric yield improvement. | Cheng Zhuo, Yung-Hsu Chang, Dennis Sylvester, David T. Blaauw |
| 2010 | Application-specific 3D Network-on-Chip design using simulated allocation. | Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar |
| 2010 | Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs. | Xin Zhao, Sung Kyu Lim |
| 2010 | On-chip power network optimization with decoupling capacitors and controlled-ESRs. | Wanping Zhang, Ling Zhang, Amirali Shayan Arani, Wenjian Yu, Xiang Hu, Zhi Zhu, A. Ege Engin, Chung-Kuan Cheng |
| 2010 | A robust pixel-based RET optimization algorithm independent of initial conditions. | Jinyu Zhang, Wei Xiong, Yan Wang, Zhiping Yu, Min-Chun Tsai |
| 2010 | On process-aware 1-D standard cell design. | Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao |
| 2010 | An extension of the generalized Hamiltonian method to | Zheng Zhang, Ngai Wong |
| 2010 | A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel. | Hao Yu, Xuexin Liu, Hai Wang, Sheldon X.-D. Tan |
| 2010 | Rapid prototyping on a structured ASIC fabric. | Steve C. L. Yuen, Yanqing Ai, Brian P. W. Chan, Thomas C. P. Chau, Sam M. H. Ho, Oscar K. L. Lau, Kong-Pang Pun, Philip Heng Wai Leong, Oliver C. S. Choy |
| 2010 | Floorplanning and topology generation for application-specific network-on-chip. | Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto |
| 2010 | Statistical timing verification for transparently latched circuits through structural graph traversal. | Xingliang Yuan, Jia Wang |
| 2010 | A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example. | W. M. Young, Chua-Huang Huang, Alan P. Su, Chewnpu Jou, Fu-Lung Hsueh |
| 2010 | Automatic constraint generation for guided random simulation. | Hu-Hsi Yeh, Chung-Yang Huang |
| 2010 | Efficient model reduction of interconnects via double gramians approximation. | Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yici Cai |
| 2010 | Obstacle-aware longest path using rectangular pattern detouring in routing grids. | Jin-Tai Yan, Ming-Ching Jhong, Zhi-Wei Chen |
| 2010 | A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography. | Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, David Z. Pan |
| 2010 | Optimizing power and performance for reliable on-chip networks. | Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan |
| 2010 | -Possibility of ESL-: a software centric system design for multicore SoC in the upstream phase. | Koichiro Yamashita |
| 2010 | Energy efficient joint scheduling and multi-core interconnect design. | Cathy Qun Xu, Chun Jason Xue, Yi He, Edwin Hsing-Mean Sha |
| 2010 | On signal tracing in post-silicon validation. | Qiang Xu, Xiao Liu |
| 2010 | CrossRouter: a droplet router for cross-referencing digital microfluidic biochips. | Zigang Xiao, Evangeline F. Y. Young |
| 2010 | Fixed-outline thermal-aware 3D floorplanning. | Linfu Xiao, Subarna Sinha, Jingyu Xu, Evangeline F. Y. Young |
| 2010 | Improved weight assignment for logic switching activity during at-speed test pattern generation. | Meng-Fan Wu, Hsin-Cheih Pan, Teng-Han Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng |
| 2010 | Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. | Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin |
| 2010 | Physical design techniques for optimizing RTA-induced variations. | Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar |