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Forum on Specification and Design Languages

FDL

C

CORE rank

CORE rank (raw)

C

Fields of research

Software Engineering

Papers indexed

774

2003–2025

Papers per year

200371 peak2025

FDL papers

774 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2013How to survive the verification of the latest generation of automotive system on chip.Arnaud Laroche, Jrme Kirscher
2013A new assertion property language for analog/mixed-signal circuits.Dhanashree Kulkarni, Andrew N. Fisher, Chris J. Myers
2013Modeling communication and circuit's behavior.Tom J. Kazmierski, Torsten Maehne
2013Systemc-clang: An open-source framework for analyzing mixed-abstraction SystemC models.Anirudh M. Kaushik, Hiren D. Patel
2013A novel approach for assertion based verification of DDR memory protocols.Moustafa Kassem, Marianne Michel, Mohamed Abdelsalam, Ashraf Salem
2013Model driven engineering at work.Gjalt de Jong, Julio L. Medina
2013Advanced features for industry-level logging and tracing of C-based designs.Wei Hong, Jyoti Joshi, Alexander Viehl, Nico Bannow, Angela Kramer, Hendrik Post, Oliver Bringmann, Wolfgang Rosenstiel
2013Design space exploration for cyber physical system design using constraint solving.Benny Hckner, Petra Hofstedt, Sascha Kaltschmidt, Peter Sauer, Thilo Vrtler
2013SystemVerilog: The new standard.Kaiming Ho
2013Combining analytical and simulation-based design space exploration for time-critical systems.Fernando Herrera, Ingo Sander
2013Systemc transaction level modeling with transaction events.Bastian Haetzer, Martin Radetzki
2013Model generation for embedded analog/mixed-signal systems.Jan Haase, Franois Pcheux
2013Hybrid dynamical systems for memristor modelling an approach avoiding the terminal-state problem.Joachim Haase, Andr Lange
2013Verification of heterogeneous systems: Theory and industrial experiences.Christoph Grimm, Emmanuelle Encrenaz
2013Code generation alternatives to reduce heterogeneous embedded systems to homogeneity.Franco Fummi, Michele Lora, Francesco Stefanni, Sara Vinco
2013Systemc infrastructure and extensions.Peter Flake, Frank Oppenheimer
2013Why SystemVeriog?Peter Flake
2013Modeling the analog circuit design feature variety.Cristian Ferent, Alex Doboli
2013Fine grained adaptive simulation with application to NoCs.Marcus Eggenberger, Martin Radetzki
2013Multi-paradigm semantics for simulating SysML models using SystemC-AMS.Daniel Chaves Cafe, Filipe Vinci dos Santos, Ccile Hardebolle, Christophe Jacquet, Frdric Boulanger
2013If SystemVerilog is so good, why do we need the UVM? Sharing responsibilities between libraries and the core language.Jonathan Bromley
2013Model-driven design for the development of multi-platform smartphone applications.G. Botturi, Emad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia
2013Application of formal methods for design space exploration and refinement.Dominique Borrione, Ashraf M. Salem
2013Platform based design.Jean-Philippe Babau, Martin Radetzki
2012Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic.Clifford Wolf, Johann Glaser, Florian Schupfer, Jan Haase, Christoph Grimm
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