| 2026 | DATE | Polynomial Verification of 2-Affine Spaces. | Anna Bernasconi, Valentina Ciriani, Gianmarco Cuciniello, Caroline Dominik, Rolf Drechsler |
| 2026 | DATE | Late Breaking Results: Efficient Formal Verification of Highly Optimized MAC Units. | Jan Kleinekathfer, Lennart Weingarten, Kamalika Datta, Rolf Drechsler |
| 2026 | DATE | Late Breaking Results: PolyRAD - Polynomial Formal Verification of Restoring Array Dividers. | Mohamed A. Nadeem, Chandan Kumar Jha, Rolf Drechsler |
| 2026 | DATE | Late Breaking Results: Conversion of Neural Networks into Logic Flows for Edge Computing. | Daniel Stein, Shaoyi Huang, Rolf Drechsler, Bing Li, Grace Li Zhang |
| 2026 | DATE | Identifying Hardware Optimizations for Neural Network Inference using Virtual Prototypes. | Jan Zielasko, Rolf Drechsler |
| 2026 | DDECS | Security-Aware Benchmarks for Performance Exploration of CHERI-Enabled Architectures. | Spandan Das, Sayak Deb, Khushboo Qayyum, Sallar Ahmadi-Pour, Christoph Lth, Rolf Drechsler |
| 2026 | DDECS | Measurement-Driven Adaptive Low-Overhead Implementation of Multi-Controlled Toffoli Gates. | Abhoy Kole, Till Schnittka, Rolf Drechsler |
| 2026 | DDECS | Approximated MAGIC-ReRAM Adder Circuits for Low-Latency In-Memory Computing. | Saeideh Nabipour, Chandan Kumar Jha, Saeideh Shirinzadeh, Rolf Drechsler |
| 2026 | DDECS | Fan-In Aware Graph-Based Optimization for MAC-Based in-Memory Computing. | Fatemeh Shirinzadeh, Abhoy Kole, Kamalika Datta, Saeideh Shirinzadeh, Rolf Drechsler |
| 2026 | ETS | Special Session: Hardware Security at the Circuit and Layout Levels. | Sajjad Parvin, Carl Riehm, Nan Du, Ralf Brederlow, Frank Sill Torres, Rolf Drechsler |
| 2026 | ETS | Path Delay Fault Testable KFDD Circuits with Polynomial Test Pattern Generation. | Martha Schnieber, Rolf Drechsler |
| 2025 | DATE | FrEDDY: Modular and Efficient Framework to Engineer Decision Diagrams Yourself. | Rune Krauss, Jan Zielasko, Rolf Drechsler |
| 2025 | DATE | Polynomial Formal Verification of Sequential Circuits Using Weighted-AIGs. | Mohamed A. Nadeem, Chandan Kumar Jha, Rolf Drechsler |
| 2025 | DATE | CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design. | Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li |
| 2025 | DATE | Accurate and Extensible Symbolic Execution of Binary Code Based on Formal ISA Semantics. | Sren Tempel, Tobias Brandt, Christoph Lth, Christian Dietrich, Rolf Drechsler |
| 2025 | DATE | Late Breaking Results: Towards Efficient Formal Verification of Dot Product Architectures. | Lennart Weingarten, Kamalika Datta, Rolf Drechsler |
| 2025 | DDECS | Towards an Automated Debugging Approach for Fault Identification in Quantum Circuits. | Anton Maidl, Abhoy Kole, Kamalika Datta, Jannis Stoppe, Rolf Drechsler |
| 2025 | DDECS | CrosSym: Cross-Level Verification of SystemC Peripherals using Symbolic Execution. | Karl Aaron Rudkowski, Sallar Ahmadi-Pour, Rolf Drechsler |
| 2025 | DDECS | River: Sneak Path Aware READ-based In-Memory Computing for 1T1M Memristive Crossbars. | Till Schnittka, Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler |
| 2025 | DDECS | LLM-assisted Performance Estimation of Embedded Software on RISC-V Processors. | Weiyan Zhang, Muhammad Hassan, Rolf Drechsler |
| 2025 | DSD | Automatic Polynomial Formal Verification of a Floating-Point Multiplier. | Jan Kleinekathfer, Rolf Drechsler |
| 2025 | DSD | Synthesis for Testability: Polynomial Test Pattern Generation for KFDD Circuits. | Martha Schnieber, Rolf Drechsler |
| 2025 | DSD | A Comprehensive Synthesis and Verification Approach for RRAM-Based Neuromorphic Computing. | Fatemeh Shirinzadeh, Abhoy Kole, Kamalika Datta, Saeideh Shirinzadeh, Rolf Drechsler |
| 2025 | ETS | Large Language Models (LLMs) for Verification, Testing, and Design. | Chandan Kumar Jha, Muhammad Hassan, Khushboo Qayyum, Sallar Ahmadi-Pour, Kangwei Xu, Ruidi Qiu, Jason Blocklove, Luca Collini, Andre Nakkab, Ulf Schlichtmann, Grace Li Zhang, Ramesh Karri, Bing Li, Siddharth Garg, Rolf Drechsler |
| 2025 | ETS | European Test Symposium Teams: an Anniversary Snapshot. | Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilrd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersgl, Grschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard, Marcello Traiola, Arnaud Virazel, Fernando Fernandes dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letcia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, Fabian Luis Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand |
| 2025 | FDL | BDD Meets SAT: Binary Hybrid Diagrams for Efficient Generation of Multiple Solutions. | Rune Krauss, Luca Mller, Marius Marach, Rolf Drechsler |
| 2025 | FDL | System-Level Design Space Exploration for Matrix Multiplication using Compute-In-Memory Unit. | Deepak Ravibabu, Sallar Ahmadi-Pour, Muhammad Hassan, Abhoy Kole, Chandan Kumar Jha, Rolf Drechsler |
| 2025 | FDL | ForMAt: Formal Verification of Scalable Multiply and Accumulate Units. | Lennart Weingarten, Kamalika Datta, Rolf Drechsler |
| 2024 | ASPDAC | Security Coverage Metrics for Information Flow at the System Level. | Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler |
| 2024 | ASPDAC | MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. | Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant |
| 2024 | CEC | Finding the perfect MRI sequence for your patient - Towards an optimisation workflow for MRI-sequences. | Christina Plump, Daniel Christopher Hoinkiss, Jrn Huber, Bernhard J. Berger, Matthias Gnther, Christoph Lth, Rolf Drechsler |
| 2024 | DAC | Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent. | Kemal aglar Coskun, Muhammad Hassan, Lars Hedrich, Rolf Drechsler |
| 2024 | DAC | Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification. | Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler |
| 2024 | DATE | LLM-Guided Formal Verification Coupled with Mutation Testing. | Muhammad Hassan, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha, Rolf Drechsler |
| 2024 | DATE | Polynomial Formal Verification of Sequential Circuits. | Caroline Dominik, Rolf Drechsler |
| 2024 | DATE | Dynamic Realization of Multiple Control Toffoli Gate. | Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler |
| 2024 | DATE | Hidden Cost of Circuit Design with RFETs. | Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler |
| 2024 | DATE | Complete and Efficient Verification for a RISC-V Processor Using Formal Verification. | Lennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler |
| 2024 | DDECS | Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences. | Jan Zielasko, Rune Krauss, Marcel Merten, Rolf Drechsler |
| 2024 | DSD | SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth. | Luca Mller, Rolf Drechsler |
| 2024 | ETS | A Multi-Objective Evolutionary Approach for Test Network Design. | Payam Habiby, Fatemeh Shirinzadeh, Sebastian Huhn, Rolf Drechsler |
| 2024 | ETS | Polynomial Formal Verification of Approximate Adders with Constant Cutwidth. | Mohamed A. Nadeem, Chandan Kumar Jha, Rolf Drechsler |
| 2023 | ASPDAC | Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars. | Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler |
| 2023 | ASPDAC | EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation. | Rune Krauss, Mehran Goli, Rolf Drechsler |
| 2023 | ASPDAC | Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study. | Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler |
| 2023 | CEC | EVOAL: A Domain-Specific Language-Based Approach to Optimisation. | Bernhard J. Berger, Christina Plump, Rolf Drechsler |
| 2023 | DATE | Processor Verification using Symbolic Execution: A RISC-V Case-Study. | Niklas Bruns, Vladimir Herdt, Rolf Drechsler |
| 2023 | DATE | Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits. | Kemal aglar Coskun, Muhammad Hassan, Rolf Drechsler |
| 2023 | DATE | Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex Circuits. | Rolf Drechsler, Alireza Mahzoon |
| 2023 | DATE | Polynomial Formal Verification of Floating Point Adders. | Jan Kleinekathfer, Alireza Mahzoon, Rolf Drechsler |
| 2023 | DATE | Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network. | Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler |
| 2023 | DATE | FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing. | Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler |
| 2023 | DATE | Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors. | Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed E. Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, Violetta Sessi, M. Drescher, S. Kolodinski, M. Wiatr |
| 2023 | DDECS | Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes. | Rune Krauss, Mehran Goli, Rolf Drechsler |
| 2023 | DDECS | Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques. | Marcel Merten, Muhammad Hassan, Rolf Drechsler |
| 2023 | DSD | Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors. | Weiyan Zhang, Mehran Goli, Muhammad Hassan, Rolf Drechsler |
| 2023 | ETS | Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips. | Payam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn, Rolf Drechsler |
| 2023 | ETS | Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods. | Marcel Merten, Sebastian Huhn, Rolf Drechsler |
| 2023 | FDL | Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification. | Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler |
| 2023 | FDL | Hybrid PTX Analysis for GPU accelerated CNN inferencing aiding Computer Architecture Design. | Christopher A. Metz, Christina Plump, Bernhard J. Berger, Rolf Drechsler |
| 2023 | FDL | Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models. | Sren Tempel, Tobias Brandt, Christoph Lth, Rolf Drechsler |
| 2022 | ASPDAC | Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques. | Sajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler |
| 2022 | ASPDAC | Automated Detection of Spatial Memory Safety Violations for Constrained Devices. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2022 | ATVA | SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2022 | CEC | Using density of training data to improve evolutionary algorithms with approximative fitness functions. | Christina Plump, Bernhard J. Berger, Rolf Drechsler |
| 2022 | DAC | Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. | Alireza Mahzoon, Daniel Groe, Christoph Scholl, Alexander Konrad, Rolf Drechsler |
| 2022 | DAC | Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. | Pascal Pieper, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2022 | DATE | Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging. | Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler |
| 2022 | DATE | The Scale4Edge RISC-V Ecosystem. | Wolfgang Ecker, Peer Adelt, Wolfgang Mller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jrg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz |
| 2022 | DATE | LiM-HDL: HDL-Based Synthesis for In-Memory Computing. | Saman Frhlich, Rolf Drechsler |
| 2022 | DDECS | Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters. | Kemal aglar Coskun, Muhammad Hassan, Rolf Drechsler |
| 2022 | DDECS | Towards Polynomial Formal Verification of Complex Arithmetic Circuits. | Rolf Drechsler, Alireza Mahzoon, Mehran Goli |
| 2022 | DDECS | Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions. | Milan Funck, Vladimir Herdt, Rolf Drechsler |
| 2022 | DDECS | ML-based Power Estimation of Convolutional Neural Networks on GPGPUs. | Christopher A. Metz, Mehran Goli, Rolf Drechsler |
| 2022 | DDECS | Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression. | Weiyan Zhang, Mehran Goli, Rolf Drechsler |
| 2022 | DSD | Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study. | Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler, Klaus D. McDonald-Maier |
| 2022 | DSD | Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles. | Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta, Rolf Drechsler |
| 2022 | DSD | Generation of Verified Programs for In-Memory Computing. | Saman Frhlich, Rolf Drechsler |
| 2022 | DSD | SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library. | Abhoy Kole, Kamalika Datta, Indranil Sengupta, Rolf Drechsler |
| 2022 | DSD | Polynomial Formal Verification of Approximate Adders. | Martha Schnieber, Saman Frhlich, Rolf Drechsler |
| 2022 | ETS | Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods. | Marcel Merten, Sebastian Huhn, Rolf Drechsler |
| 2022 | FDL | Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification. | Niklas Bruns, Vladimir Herdt, Rolf Drechsler |
| 2022 | FDL | Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device. | Alexander Fratzer, Vladimir Herdt, Christoph Lth, Rolf Drechsler |
| 2021 | ASPDAC | System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations. | Muhammad Hassan, Daniel Groe, Rolf Drechsler |
| 2021 | ASPDAC | ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs. | Mehran Goli, Rolf Drechsler |
| 2021 | ASPDAC | Mutation-based Compliance Testing for RISC-V. | Vladimir Herdt, Sren Tempel, Daniel Groe, Rolf Drechsler |
| 2021 | ASPDAC | One-pass Synthesis for Field-coupled Nanocomputing Technologies. | Marcel Walter, Winston Haaswijk, Robert Wille, Frank Sill Torres, Rolf Drechsler |
| 2021 | CEC | Improving Evolutionary Algorithms by Enhancing an Approximative Fitness Function through Prediction Intervals. | Christina Plump, Bernhard J. Berger, Rolf Drechsler |
| 2021 | CEC | Domain-driven Correlation-aware Recombination and Mutation Operators for Complex Real-world Applications. | Christina Plump, Bernhard J. Berger, Rolf Drechsler |
| 2021 | DAC | Late Breaking Results: Polynomial Formal Verification of Fast Adders. | Alireza Mahzoon, Rolf Drechsler |
| 2021 | DAC | Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2021 | DATE | Combining SWAPs and Remote Toffoli Gates in the Mapping to IBM QX Architectures. | Philipp Niemann, Chandan Bandyopadhyay, Rolf Drechsler |
| 2021 | DATE | System Level Verification of Phase-Locked Loop using Metamorphic Relations. | Muhammad Hassan, Daniel Groe, Rolf Drechsler |
| 2021 | DATE | Nano Security: From Nano-Electronics to Secure Systems. | Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Gneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer |
| 2021 | DATE | Vertical IP Protection of the Next-Generation Devices: Quo Vadis? | Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar |
| 2021 | DATE | Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization. | Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Groe, Rolf Drechsler |
| 2021 | DATE | An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2021 | DDECS | PolyAdd: Polynomial Formal Verification of Adder Circuits. | Rolf Drechsler |
| 2021 | DSD | Automated Debugging-Aware Visualization Technique for SystemC HLS Designs. | Mehran Goli, Alireza Mahzoon, Rolf Drechsler |
| 2021 | DSD | Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation. | Philipp Niemann, Luca Mller, Rolf Drechsler |
| 2021 | FDL | RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems. | Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler |
| 2021 | FDL | VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes. | Mehran Goli, Rolf Drechsler |
| 2021 | FDL | In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2020 | ASPDAC | Towards Automatic Hardware Synthesis from Formal Specification to Implementation. | Fritjof Bornebusch, Christoph Lth, Robert Wille, Rolf Drechsler |
| 2020 | ATVA | RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms. | Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DAC | Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side | Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DAC | Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. | Pascal Pieper, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DAC | Verification for Field-coupled Nanocomputing Circuits. | Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Groe, Rolf Drechsler |
| 2020 | DATE | Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes | Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DATE | Towards Specification and Testing of RISC-V ISA Compliance | Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DATE | Towards Formal Verification of Optimized and Industrial Multipliers. | Alireza Mahzoon, Daniel Groe, Christoph Scholl, Rolf Drechsler |
| 2020 | DATE | Verification Runtime Analysis: Get the Most Out of Partial Verification. | Martin Ring, Fritjof Bornebusch, Christoph Lth, Robert Wille, Rolf Drechsler |
| 2020 | DDECS | Towards Generation of a Programmable Power Management Unit at the Electronic System Level. | David Lemma, Mehran Goli, Daniel Groe, Rolf Drechsler |
| 2020 | DSD | Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials. | Rolf Drechsler, Sebastian Huhn, Christina Plump |
| 2020 | DSD | ToPoliNano and fiction: Design Tools for Field-coupled Nanocomputing. | Umberto Garlando, Marcel Walter, Robert Wille, Fabrizio Riente, Frank Sill Torres, Rolf Drechsler |
| 2020 | DSD | Design Space Exploration in the Mapping of Reversible Circuits to IBM Quantum Computers. | Philipp Niemann, Alexandre A. A. de Almeida, Gerhard W. Dueck, Rolf Drechsler |
| 2020 | FDL | Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. | Vladimir Herdt, Daniel Groe, Eyck Jentzsch, Rolf Drechsler |
| 2019 | ASPDAC | Maximizing power state cross coverage in firmware-based power management. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2019 | ASPDAC | Scalable design for field-coupled nanocomputing circuits. | Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Groe, Rolf Drechsler |
| 2019 | DAC | Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study. | Vladimir Herdt, Daniel Groe, Hoang M. Le, Rolf Drechsler |
| 2019 | DAC | RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. | Alireza Mahzoon, Daniel Groe, Rolf Drechsler |
| 2019 | DAC | Temporal Tracing of On-Chip Signals using Timeprints. | Rehab Massoud, Hoang M. Le, Peter Chini, Prakash Saivasan, Roland Meyer, Rolf Drechsler |
| 2019 | DATE | One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing. | Saman Frhlich, Daniel Groe, Rolf Drechsler |
| 2019 | DATE | Data Flow Testing for SystemC-AMS Timed Data Flow Models. | Muhammad Hassan, Daniel Groe, Hoang M. Le, Rolf Drechsler |
| 2019 | DATE | Verifying Instruction Set Simulators using Coverage-guided Fuzzing | Vladimir Herdt, Daniel Groe, Hoang M. Le, Rolf Drechsler |
| 2019 | DATE | Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing. | Hoang M. Le, Daniel Groe, Niklas Bruns, Rolf Drechsler |
| 2019 | DATE | Better Late Than Never : Verification of Embedded Systems After Deployment. | Martin Ring, Fritjof Bornebusch, Christoph Lth, Robert Wille, Rolf Drechsler |
| 2019 | DATE | Accuracy and Compactness in Decision Diagrams for Quantum Computation. | Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille |
| 2019 | DSD | Code is Ethics - Formal Techniques for a Better World. | Rolf Drechsler, Christoph Lth |
| 2019 | DSD | Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes. | Mehran Goli, Rolf Drechsler |
| 2019 | DSD | Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents. | Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2019 | DSD | SAT-Hard: A Learning-Based Hardware SAT-Solver. | Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Groe, Rolf Drechsler |
| 2019 | ETS | Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns. | Sebastian Huhn, Daniel Tille, Rolf Drechsler |
| 2019 | ETS | Machine Learning-based Prediction of Test Power. | Harshad Dhotre, Stephan Eggersgl, Krishnendu Chakrabarty, Rolf Drechsler |
| 2019 | FDL | Functional Coverage-Driven Characterization of RF Amplifiers. | Muhammad Hassan, Daniel Groe, Thilo Vrtler, Karsten Einwich, Rolf Drechsler |
| 2019 | FDL | Systematic RISC-V based Firmware Design | Vladimir Herdt, Daniel Groe, Rolf Drechsler, Christoph Gerum, Alexander Louis-Ferdinand Jung, Joscha Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz |
| 2018 | ASPDAC | Approximation-aware testing for approximate circuits. | Arun Chandrasekharan, Stephan Eggersgl, Daniel Groe, Rolf Drechsler |
| 2018 | DATE | Approximate hardware generation using symbolic computer algebra employing grobner basis. | Saman Frhlich, Daniel Groe, Rolf Drechsler |
| 2018 | DATE | Testbench qualification for SystemC-AMS timed data flow models. | Muhammad Hassan, Daniel Groe, Hoang M. Le, Thilo Vrtler, Karsten Einwich, Rolf Drechsler |
| 2018 | DATE | Towards fully automated TLM-to-RTL property refinement. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2018 | DATE | Resilience evaluation via symbolic fault injection on intermediate code. | Hoang M. Le, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2018 | DATE | Improved synthesis of Clifford+T quantum functionality. | Philipp Niemann, Robert Wille, Rolf Drechsler |
| 2018 | DATE | An exact method for design exploration of quantum-dot cellular automata. | Marcel Walter, Robert Wille, Daniel Groe, Frank Sill Torres, Rolf Drechsler |
| 2018 | DDECS | Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing. | Harshad Dhotre, Stephan Eggersgl, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen |
| 2018 | DDECS | Natural Language Based Power Domain Partitioning. | David Lemma, Daniel Groe, Rolf Drechsler |
| 2018 | DSD | Towards Reversed Approximate Hardware Design. | Saman Frhlich, Daniel Groe, Rolf Drechsler |
| 2018 | DSD | Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata. | Frank Sill Torres, Pedro Arthur Silva, Geraldo Fontes, Jos Augusto Miranda Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Rolf Drechsler |
| 2018 | DSD | Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata. | Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Groe, Rolf Drechsler |
| 2018 | FDL | Extensible and Configurable RISC-V Based Virtual Prototype. | Vladimir Herdt, Daniel Groe, Hoang M. Le, Rolf Drechsler |
| 2018 | FDL | Automatic Design of Microfluidic Devices. | Robert Wille, Bing Li, Rolf Drechsler, Ulf Schlichtmann |
| 2017 | ASPDAC | Enhancing robustness of sequential circuits using application-specific knowledge and formal methods. | Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler |
| 2017 | ASPDAC | Exact routing for micro-electrode-dot-array digital microfluidic biochips. | Oliver Keszcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler |
| 2017 | ASPDAC | Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. | Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Groe, Rolf Drechsler |
| 2017 | DATE | Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications. | Mehran Goli, Jannis Stoppe, Rolf Drechsler |
| 2017 | DATE | Data flow testing for virtual prototypes. | Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Groe, Rolf Drechsler |
| 2017 | DATE | Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. | Sebastian Huhn, Stephan Eggersgl, Krishnendu Chakrabarty, Rolf Drechsler |
| 2017 | DATE | Effects of cell shapes on the routability of Digital Microfluidic Biochips. | Leonard Schneider, Oliver Keszcze, Jannis Stoppe, Rolf Drechsler |
| 2017 | DATE | Endurance management for resistive Logic-In-Memory computing architectures. | Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler |
| 2017 | ETS | Foreword. | Maria K. Michael, Rolf Drechsler, Stephan Eggersgl, Haralampos-G. D. Stratigopoulos, Sybille Hellebrand, Rob Aitken |
| 2017 | FDL | Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2017 | FDL | Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2016 | ASPDAC | BDD minimization for approximate computing. | Mathias Soeken, Daniel Groe, Arun Chandrasekharan, Rolf Drechsler |
| 2016 | ASPDAC | Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits. | Robert Wille, Oliver Keszcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler |
| 2016 | CAV | ParCoSS: Efficient Parallelized Compiled Symbolic Simulation. | Vladimir Herdt, Hoang Minh Le, Daniel Groe, Rolf Drechsler |
| 2016 | DAC | Precise error determination of approximated components in sequential circuits with model checking. | Arun Chandrasekharan, Mathias Soeken, Daniel Groe, Rolf Drechsler |
| 2016 | DAC | An MIG-based compiler for programmable logic-in-memory architectures. | Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amar, Rolf Drechsler, Giovanni De Micheli |
| 2016 | DATE | Quantitative timing analysis of UML activity diagrams using statistical model checking. | Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Groe, Rolf Drechsler |
| 2016 | DATE | Towards formal verification of real-world SystemC TLM peripheral models - a case study. | Hoang Minh Le, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2016 | DATE | Formal verification of integer multipliers by combining Grbner basis with logic reduction. | Amr A. R. Sayed-Ahmed, Daniel Groe, Ulrich Khne, Mathias Soeken, Rolf Drechsler |
| 2016 | DATE | Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. | Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler |
| 2016 | DDECS | Multi-objective BDD optimization for RRAM based circuit design. | Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler |
| 2016 | ETS | VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers. | Sebastian Huhn, Stephan Eggersgl, Rolf Drechsler |
| 2016 | FDL | On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2016 | FDL | Change impact analysis for hardware designs from natural language to system level. | Martin Ring, Jannis Stoppe, Christoph Lth, Rolf Drechsler |
| 2015 | ASPDAC | Determining the minimal number of swap gates for multi-dimensional nearest neighbor quantum circuits. | Aaron Lye, Robert Wille, Rolf Drechsler |
| 2015 | ASPDAC | Reverse BDD-based synthesis for splitter-free optical circuits. | Robert Wille, Oliver Keszcze, Clemens Hopfmuller, Rolf Drechsler |
| 2015 | ATVA | Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules. | Vladimir Herdt, Hoang Minh Le, Daniel Groe, Rolf Drechsler |
| 2015 | DAC | Verifying SystemC using stateful symbolic simulation. | Vladimir Herdt, Hoang Minh Le, Rolf Drechsler |
| 2015 | DAC | A generic representation of CCSL time constraints for UML/MARTE models. | Judith Peters, Robert Wille, Nils Przigoda, Ulrich Khne, Rolf Drechsler |
| 2015 | DATE | Automated feature localization for dynamically generated SystemC designs. | Jannis Stoppe, Robert Wille, Rolf Drechsler |
| 2015 | DDECS | Requirement Phrasing Assistance Using Automatic Quality Assessment. | Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler |
| 2015 | DDECS | Contradiction Analysis for Inconsistent Formal Models. | Nils Przigoda, Robert Wille, Rolf Drechsler |
| 2015 | DSD | Verification-Driven Design Across Abstraction Levels: A Case Study. | Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler |
| 2015 | DSD | Leveraging the Analysis for Invariant Independence in Formal System Models. | Nils Przigoda, Robert Wille, Rolf Drechsler |
| 2014 | ASPDAC | Efficient synthesis of quantum circuits implementing clifford group operations. | Philipp Niemann, Robert Wille, Rolf Drechsler |
| 2014 | ASPDAC | Optimal SWAP gate insertion for nearest neighbor quantum circuits. | Robert Wille, Aaron Lye, Rolf Drechsler |
| 2014 | DAC | Exact One-pass Synthesis of Digital Microfluidic Biochips. | Oliver Keszcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler |
| 2014 | DAC | Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. | Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Grttner, Thomas Kruse, Christoph Kuznik, Hoang Minh Le, Andreas Mauderer, Wolfgang Mller, Daniel Mller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl |
| 2014 | DATE | Panel: Future SoC verification methodology: UVM evolution or revolution? | Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan J. Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev |
| 2014 | DATE | Towards verifying determinism of SystemC designs. | Hoang Minh Le, Rolf Drechsler |
| 2014 | DDECS | Optimizing DD-based synthesis of reversible circuits using negative control lines. | Eleonora Schnborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler |
| 2014 | DSD | Improving Coverage of Simulation-Based Verification by Dedicated Stimuli Generation. | Shuo Yang, Robert Wille, Rolf Drechsler |
| 2014 | ETS | Optimization-based multiple target test generation for highly compacted test sets. | Stephan Eggersgl, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler |
| 2014 | FDL | Verifying consistency between activity diagrams and their corresponding OCL contracts. | Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Khne, Rolf Drechsler |
| 2014 | FDL | MetaSMT: a unified interface to SMT-LIB2. | Heinz Riener, Mathias Soeken, Clemens Werther, Grschwin Fey, Rolf Drechsler |
| 2014 | FDL | Automatic refinement checking for formal system models. | Julia Seiter, Robert Wille, Ulrich Khne, Rolf Drechsler |
| 2014 | FDL | Automating the translation of assertions using natural language processing techniques. | Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris, Rolf Drechsler |
| 2013 | ASPDAC | Improving the mapping of reversible circuits to quantum circuits using multiple target lines. | Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler |
| 2013 | DAC | Verifying SystemC using an intermediate verification language and symbolic simulation. | Hoang Minh Le, Daniel Groe, Vladimir Herdt, Rolf Drechsler |
| 2013 | DATE | Scalable fault localization for SystemC TLM designs. | Hoang Minh Le, Daniel Groe, Rolf Drechsler |
| 2013 | DATE | Determining relevant model elements for the verification of UML/OCL specifications. | Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler |
| 2013 | DATE | Towards a generic verification methodology for system models. | Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler |
| 2013 | DDECS | Hardware-Software Co-Visualization: Developing systems in the holodeck. | Rolf Drechsler, Mathias Soeken |
| 2013 | DSD | Cone of Influence Analysis at the Electronic System Level Using Machine Learning. | Jannis Stoppe, Robert Wille, Rolf Drechsler |
| 2013 | DSD | Minimal Stimuli Generation in Simulation-Based Verification. | Shuo Yang, Robert Wille, Daniel Groe, Rolf Drechsler |
| 2012 | ASPDAC | Synthesis of reversible circuits with minimal lines for large functions. | Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| 2012 | DATE | A guiding coverage metric for formal verification. | Finn Haedicke, Daniel Groe, Rolf Drechsler |
| 2012 | DATE | Eliminating invariants in UML/OCL models. | Mathias Soeken, Robert Wille, Rolf Drechsler |
| 2012 | DATE | Automatic design of low-power encoders using reversible circuit synthesis. | Robert Wille, Rolf Drechsler, Christof Osewold, Alberto Garca Ortiz |
| 2012 | DATE | Debugging of inconsistent UML/OCL models. | Robert Wille, Mathias Soeken, Rolf Drechsler |
| 2012 | DDECS | A new SAT-based ATPG for generating highly compacted test sets. | Stephan Eggersgl, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler |
| 2012 | DSD | Coverage-Driven Stimuli Generation. | Shuo Yang, Robert Wille, Daniel Groe, Rolf Drechsler |
| 2012 | FDL | Formal Specification Level: Towards verification-driven design based on natural language processing. | Rolf Drechsler, Mathias Soeken, Robert Wille |
| 2012 | FDL | Formal Specification Level. | Rolf Drechsler, Mathias Soeken, Robert Wille |
| 2012 | FDL | Localizing features of ESL models for design understanding. | Marc Michael, Daniel Groe, Rolf Drechsler |
| 2011 | DATE | As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization. | Stephan Eggersgl, Rolf Drechsler |
| 2011 | DATE | Verifying dynamic aspects of UML models. | Mathias Soeken, Robert Wille, Rolf Drechsler |
| 2011 | DATE | Determining the minimal number of lines for large reversible circuits. | Robert Wille, Oliver Keszcze, Rolf Drechsler |
| 2011 | DDECS | TLM protocol compliance checking at the Electronic System Level. | Mohamed Bawadekji, Daniel Groe, Rolf Drechsler |
| 2011 | DDECS | Automatic property generation for the formal verification of bus bridges. | Mathias Soeken, Ulrich Khne, Martin Freibothe, Grschwin Fey, Rolf Drechsler |
| 2011 | FDL | Analyzing dependability measures at the Electronic System Level. | Marc Michael, Daniel Groe, Rolf Drechsler |
| 2011 | FDL | Efficient realization of control logic in reversible circuits. | Sebastian Offermann, Robert Wille, Rolf Drechsler |
| 2010 | DAC | Reducing the number of lines in reversible circuits. | Robert Wille, Mathias Soeken, Rolf Drechsler |
| 2010 | DATE | Verifying UML/OCL models using Boolean satisfiability. | Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| 2010 | DDECS | Formal verification meets robustness checking - Techniques and challenges. | Rolf Drechsler, Grschwin Fey |
| 2010 | DDECS | A better-than-worst-case robustness measure. | Stefan Frehse, Grschwin Fey, Rolf Drechsler |
| 2010 | DDECS | Synthesizing multiplier in reversible logic. | Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| 2010 | DDECS | Window optimization of reversible and quantum circuits. | Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| 2010 | DSD | RobuCheck: A Robustness Checker for Digital Circuits. | Stefan Frehse, Grschwin Fey, Andr Slflow, Rolf Drechsler |
| 2010 | EDCC | RobuCheck: a robustness checker for digital circuits. | Stefan Frehse, Grschwin Fey, Andr Slflow, Rolf Drechsler |
| 2010 | ETS | Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. | Daniel Tille, Stephan Eggersgl, Rene Krenz-Baath, Jrgen Schlffel, Rolf Drechsler |
| 2009 | DAC | Computing bounds for fault tolerance using formal techniques. | Grschwin Fey, Andr Slflow, Rolf Drechsler |
| 2009 | DAC | BDD-based synthesis of reversible logic for large functions. | Robert Wille, Rolf Drechsler |
| 2009 | DATE | Overcoming limitations of the SystemC data introspection. | Christian Genz, Rolf Drechsler |
| 2009 | DATE | Property analysis and design understanding. | Ulrich Khne, Daniel Groe, Rolf Drechsler |
| 2009 | DATE | Increasing the accuracy of SAT-based debugging. | Andr Slflow, Grschwin Fey, Ccile Braunstein, Ulrich Khne, Rolf Drechsler |
| 2009 | DATE | Debugging of Toffoli networks. | Robert Wille, Daniel Groe, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
| 2009 | DDECS | A fast untestability proof for SAT-based ATPG. | Daniel Tille, Rolf Drechsler |
| 2009 | DSD | Robustness Check for Multiple Faults Using Formal Techniques. | Stefan Frehse, Grschwin Fey, Andr Slflow, Rolf Drechsler |
| 2009 | ETS | Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. | Stephan Eggersgl, Rolf Drechsler |
| 2009 | FDL | SMT-based stimuli generation in the SystemC Verification library. | Robert Wille, Daniel Groe, Finn Haedicke, Rolf Drechsler |
| 2008 | ASPDAC | Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival. | Sujan Pandey, Rolf Drechsler |
| 2008 | DATE | Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. | Sujan Pandey, Rolf Drechsler |
| 2008 | DATE | Automatic Generation of Complex Properties for Hardware Designs. | Frank Rogin, Thomas Klotz, Grschwin Fey, Rolf Drechsler, Steffen Rlke |
| 2008 | DDECS | Incremental SAT Instance Generation for SAT-based ATPG. | Daniel Tille, Rolf Drechsler |
| 2008 | DSD | Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. | Robert Wille, Grschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler |
| 2008 | FDL | Contradiction Analysis for Constraint-based Random Simulation. | Daniel Groe, Robert Wille, Robert Siegmund, Rolf Drechsler |
| 2008 | FDL | Debugging Contradictory Constraints in Constraint-Based Random Simulation. | Daniel Groe, Robert Wille, Robert Siegmund, Rolf Drechsler |
| 2007 | DATE | Estimating functional coverage in bounded model checking. | Daniel Groe, Ulrich Khne, Rolf Drechsler |
| 2007 | DDECS | Instance Generation for SAT-based ATPG. | Daniel Tille, Grschwin Fey, Rolf Drechsler |
| 2007 | DSD | On the Construction of Small Fully Testable Circuits with Low Depth. | Grschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
| 2007 | DSD | Proving Completeness of Properties in Formal Verification of Counting Heads for Railways. | Sebastian Kinder, Rolf Drechsler |
| 2007 | EMO | Robust Multi-Objective Optimization in High Dimensional Spaces. | Andr Slflow, Nicole Drechsler, Rolf Drechsler |
| 2007 | FDL | Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. | Daniel Groe, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler |
| 2007 | FDL | An Integrated SystemC Debugging Environment. | Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rlke |
| 2006 | DATE | Efficient minimization of fully testable 2-SPP networks. | Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa |
| 2006 | DATE | Avoiding false negatives in formal verification for protocol-driven blocks. | Grschwin Fey, Daniel Groe, Rolf Drechsler |
| 2006 | DATE | On the relation between simulation-based and SAT-based diagnosis. | Grschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler |
| 2005 | ASPDAC | Lower bounds for dynamic BDD reordering. | Rdiger Ebendt, Rolf Drechsler |
| 2005 | ASPDAC | Bridging fault testability of BDD circuits. | Junhao Shi, Grschwin Fey, Rolf Drechsler |
| 2004 | ASPDAC | Minimization of the expected path length in BDDs based on local changes. | Rdiger Ebendt, Wolfgang Gnther, Rolf Drechsler |
| 2004 | ASPDAC | Combining ordered best-first search with branch and bound for exact BDD minimization. | Rdiger Ebendt, Wolfgang Gnther, Rolf Drechsler |
| 2004 | ASPDAC | Improving simulation-based verification by means of formal methods. | Grschwin Fey, Rolf Drechsler |
| 2004 | DATE | Managing Don't Cares in Boolean Satisfiability. | Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee |
| 2004 | DSD | BDD Circuit Optimization for Path Delay Fault Testability. | Grschwin Fey, Junhao Shi, Rolf Drechsler |
| 2003 | CEC | Minimizing the number of one-paths in BDDs by an evolutionary algorithm. | Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler |
| 2003 | DATE | Combination of Lower Bounds in Exact BDD Minimization. | Rdiger Ebendt, Wolfgang Gnther, Rolf Drechsler |
| 2003 | DSD | Fast Heuristics for the Edge Coloring of Large Graphs. | Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler |
| 2003 | FDL | Efficient Automatic Visualization of SystemC Designs. | Daniel Groe, Rolf Drechsler, Lothar Linhard, Gerhard Angst |
| 2002 | DSD | Reachability Analysis for Formal Verification of SystemC. | Rolf Drechsler, Daniel Groe |
| 2002 | DSD | Recursive Bi-Partitioning of Netlists for Large Number of Partitions. | Rolf Drechsler, Wolfgang Gnther, Thomas Eschbach, Lothar Linhard, Gerhard Angst |
| 2002 | DSD | Decision Diagram Optimization Using Copy Properties. | Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler |
| 2001 | ASPDAC | Low power optimization technique for BDD mapped circuits. | Per Lindgren, Mikael Kerttu, Mitchell A. Thornton, Rolf Drechsler |
| 2001 | DATE | Spectral decision diagrams using graph transformations. | Mitchell A. Thornton, Rolf Drechsler |
| 2001 | DSD | Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. | Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Gnther |
| 2001 | DSD | Level Assignment for Displaying Combinational Logic. | Rolf Drechsler, Wolfgang Gnther, Lothar Linhard, Gerhard Angst |
| 2001 | DSD | Minimization of OPKFDDs Using Genetic Algorithms. | Migyoung Jung, Gueesang Lee, Sungju Park, Rolf Drechsler |
| 2001 | EMO | Multi-objective Optimisation Based on Relation | Nicole Drechsler, Rolf Drechsler, Bernd Becker |
| 2001 | EUROGP | Heuristic Learning Based on Genetic Programming. | Nicole Drechsler, Frank Schmiedle, Daniel Groe, Rolf Drechsler |
| 1999 | ASPDAC | Exploiting Don't Caers During Data Sequencing using Genetic Algorithms. | Rolf Drechsler, Nicole Drechsler |
| 1999 | ASPDAC | Minimization of Free BDDs. | Wolfgang Gnther, Rolf Drechsler |
| 1999 | ASPDAC | Power Consumption in XOR-Based Circuits. | Yibin Ye, Kaushik Roy, Rolf Drechsler |
| 1999 | DAC | Using Lower Bounds During Dynamic BDD Minimization. | Rolf Drechsler, Wolfgang Gnther |
| 1999 | DATE | Formal Verification of Word-Level Specifications. | Stefan Hreth, Rolf Drechsler |
| 1999 | DATE | Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities. | Mitchell A. Thornton, J. P. Williams, Rolf Drechsler, Nicole Drechsler |
| 1998 | ASPDAC | Manipulation of *BMDs. | Rolf Drechsler, Stefan Hreth |
| 1998 | ASPDAC | ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified Boolean Functions. | Gueesang Lee, Rolf Drechsler |
| 1998 | DAC | Fast Exact Minimization of BDDs. | Rolf Drechsler, Nicole Drechsler, Wolfgang Gnther |
| 1998 | DATE | Dynamic Minimization of Word-Level Decision Diagrams. | Stefan Hreth, Rolf Drechsler |
| 1997 | ASPDAC | On the representational power of bit-level and word-level decision diagrams. | Bernd Becker, Rolf Drechsler, Reinhard Enders |
| 1997 | ASPDAC | Learning heuristics for OKFDD minimization by evolutionary algorithms. | Nicole Gckel, Rolf Drechsler, Bernd Becker |
| 1997 | DATE | Testability of 2-level AND/EXOR circuits. | Rolf Drechsler, Harry Hengster, Horst Schfer, Joachim Hartmann, Bernd Becker |
| 1997 | DATE | Fast and efficient construction of BDDs by reordering based synthesis. | Andreas Hett, Rolf Drechsler, Bernd Becker |
| 1996 | DATE | A Fast Optimal Robust Path Delay Fault Testable Adder. | Bernd Becker, Rolf Drechsler, Rolf Krieger, Sudhakar M. Reddy |
| 1996 | DATE | K*BMDs: A New Data Structure for Verification. | Rolf Drechsler, Bernd Becker, Stefan Ruppertz |
| 1995 | ASPDAC | Learning heuristics by genetic algorithms. | Rolf Drechsler, Bernd Becker |
| 1995 | DATE | How many decomposition types do we need? [decision diagrams]. | Bernd Becker, Rolf Drechsler |
| 1995 | DATE | Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams. | Bernd Becker, Rolf Drechsler |
| 1995 | DATE | Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions. | Rolf Drechsler, Bernd Becker |
| 1994 | DAC | Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams. | Rolf Drechsler, Andisheh Sarabi, Michael Theobald, Bernd Becker, Marek A. Perkowski |