| 2026 | ASPDAC | A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture. | Manfred Schlgl, Andreas Hinterdorfer, Daniel Groe |
| 2026 | DATE | Late Breaking Results: Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators. | Katharina Ruep, Manfred Schlgl, Daniel Groe |
| 2026 | TACAS | QSOLE: Automatic QBF Equivalence Checking. | Peter Pfeiffer, Mark Peyrer, Daniel Groe, Martina Seidl |
| 2025 | CAV | Surfer - An Extensible Waveform Viewer. | Frans Skarman, Lucas Klemmer, Daniel Groe, Oscar Gustafsson, Kevin Laeufer |
| 2025 | DATE | Fast Interpreter-Based Instruction Set Simulation for Virtual Prototypes. | Manfred Schlgl, Daniel Groe |
| 2025 | DDECS | Boosting SW Development Efficiency with Function Lifetime Diagrams. | Christoph Hazott, Daniel Groe |
| 2025 | FDL | LLM-assisted Metamorphic Testing of Embedded Graphics Libraries. | Christoph Hazott, Daniel Groe |
| 2025 | FDL | ProtoLens: Dynamic Transaction Visualization in Virtual Prototypes. | Manfred Schlgl, Jonas Reichhardt, Daniel Groe |
| 2025 | JELIA | Refined Notions of QBF Equivalences. | Peter Pfeiffer, Daniel Groe, Martina Seidl |
| 2025 | SECRYPT | Control Flow Protection by Cryptographic Instruction Chaining. | Shahzad Ahmad, Stefan Rass, Maksim Goman, Manfred Schlgl, Daniel Groe |
| 2024 | ASPDAC | Verifying Embedded Graphics Libraries leveraging Virtual Prototypes and Metamorphic Testing. | Christoph Hazott, Florian Stgmller, Daniel Groe |
| 2024 | ASPDAC | Towards a Highly Interactive Design-Debug-Verification Cycle. | Lucas Klemmer, Daniel Groe |
| 2024 | DATE | Using Formal Verification Methods for Optimization of Circuits Under External Constraints. | Daniel Groe, Lucas Klemmer, Dominik Bonora |
| 2024 | DATE | A RISC-V "V" VP: Unlocking Vector Processing for Evaluation at the System Level. | Manfred Schlgl, Moritz Stockinger, Daniel Groe |
| 2024 | ETS | Relation Coverage: A New Paradigm for Hardware/Software Testing. | Christoph Hazott, Daniel Groe |
| 2024 | FDL | An Extensible and Flexible Methodology for Analyzing the Cache Performance of Hardware Designs. | Lucas Klemmer, Daniel Groe |
| 2024 | ICCAD | Single Instruction Isolation for RISC-V Vector Test Failures. | Manfred Schlgl, Daniel Groe |
| 2023 | DATE | Improving Design Understanding of Processors leveraging Datapath Clustering. | Katharina Ruep, Daniel Groe |
| 2023 | FDL | Enhancing Compiler-Driven HDL Design with Automatic Waveform Analysis. | Frans Skarman, Lucas Klemmer, Oscar Gustafsson, Daniel Groe |
| 2022 | ASPDAC | WAL: A Novel Waveform Analysis Language for Advanced Design Understanding and Debugging. | Lucas Klemmer, Daniel Groe |
| 2022 | DAC | Waveform-based performance analysis of RISC-V processors: late breaking results. | Lucas Klemmer, Daniel Groe |
| 2022 | DAC | Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. | Alireza Mahzoon, Daniel Groe, Christoph Scholl, Alexander Konrad, Rolf Drechsler |
| 2022 | DAC | Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. | Pascal Pieper, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2022 | ETS | SpinalFuzz: Coverage-Guided Fuzzing for SpinalHDL Designs. | Katharina Ruep, Daniel Groe |
| 2022 | FDL | Formal Verification of SUBLEQ Microcode implementing the RV32I ISA. | Lucas Klemmer, Sonja Gurtner, Daniel Groe |
| 2022 | FMCAD | Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization. | Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Groe, Rolf Drechsler |
| 2021 | ASPDAC | System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations. | Muhammad Hassan, Daniel Groe, Rolf Drechsler |
| 2021 | ASPDAC | Mutation-based Compliance Testing for RISC-V. | Vladimir Herdt, Sren Tempel, Daniel Groe, Rolf Drechsler |
| 2021 | DATE | System Level Verification of Phase-Locked Loop using Metamorphic Relations. | Muhammad Hassan, Daniel Groe, Rolf Drechsler |
| 2021 | DATE | Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization. | Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Groe, Rolf Drechsler |
| 2021 | ISCAS | XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding. | Lucas Klemmer, Saman Frhlich, Rolf Drechsler, Daniel Groe |
| 2020 | ATVA | RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms. | Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DAC | Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side | Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DAC | Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. | Pascal Pieper, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DAC | Verification for Field-coupled Nanocomputing Circuits. | Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Groe, Rolf Drechsler |
| 2020 | DATE | Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes | Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DATE | Towards Specification and Testing of RISC-V ISA Compliance | Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DATE | Towards Formal Verification of Optimized and Industrial Multipliers. | Alireza Mahzoon, Daniel Groe, Christoph Scholl, Rolf Drechsler |
| 2020 | DDECS | Towards Generation of a Programmable Power Management Unit at the Electronic System Level. | David Lemma, Mehran Goli, Daniel Groe, Rolf Drechsler |
| 2020 | FDL | Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. | Vladimir Herdt, Daniel Groe, Eyck Jentzsch, Rolf Drechsler |
| 2020 | ICCD | Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. | Vladimir Herdt, Daniel Groe, Sren Tempel, Rolf Drechsler |
| 2020 | IFM | Clustering-Guided SMT($\mathcal {L\!R\!A}$) Learning. | Tim Meywerk, Marcel Walter, Daniel Groe, Rolf Drechsler |
| 2020 | ISoLA | Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling. | Tim Meywerk, Marcel Walter, Vladimir Herdt, Jan Kleinekathfer, Daniel Groe, Rolf Drechsler |
| 2019 | ASPDAC | Maximizing power state cross coverage in firmware-based power management. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2019 | ASPDAC | Scalable design for field-coupled nanocomputing circuits. | Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Groe, Rolf Drechsler |
| 2019 | DAC | Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study. | Vladimir Herdt, Daniel Groe, Hoang M. Le, Rolf Drechsler |
| 2019 | DAC | RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. | Alireza Mahzoon, Daniel Groe, Rolf Drechsler |
| 2019 | DATE | One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing. | Saman Frhlich, Daniel Groe, Rolf Drechsler |
| 2019 | DATE | Data Flow Testing for SystemC-AMS Timed Data Flow Models. | Muhammad Hassan, Daniel Groe, Hoang M. Le, Rolf Drechsler |
| 2019 | DATE | Verifying Instruction Set Simulators using Coverage-guided Fuzzing | Vladimir Herdt, Daniel Groe, Hoang M. Le, Rolf Drechsler |
| 2019 | DATE | Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing. | Hoang M. Le, Daniel Groe, Niklas Bruns, Rolf Drechsler |
| 2019 | DSD | Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents. | Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2019 | DSD | SAT-Hard: A Learning-Based Hardware SAT-Solver. | Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Groe, Rolf Drechsler |
| 2019 | FDL | Functional Coverage-Driven Characterization of RF Amplifiers. | Muhammad Hassan, Daniel Groe, Thilo Vrtler, Karsten Einwich, Rolf Drechsler |
| 2019 | FDL | Systematic RISC-V based Firmware Design | Vladimir Herdt, Daniel Groe, Rolf Drechsler, Christoph Gerum, Alexander Louis-Ferdinand Jung, Joscha Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz |
| 2018 | ASPDAC | Approximation-aware testing for approximate circuits. | Arun Chandrasekharan, Stephan Eggersgl, Daniel Groe, Rolf Drechsler |
| 2018 | DATE | Approximate hardware generation using symbolic computer algebra employing grobner basis. | Saman Frhlich, Daniel Groe, Rolf Drechsler |
| 2018 | DATE | Testbench qualification for SystemC-AMS timed data flow models. | Muhammad Hassan, Daniel Groe, Hoang M. Le, Thilo Vrtler, Karsten Einwich, Rolf Drechsler |
| 2018 | DATE | Towards fully automated TLM-to-RTL property refinement. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2018 | DATE | Resilience evaluation via symbolic fault injection on intermediate code. | Hoang M. Le, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2018 | DATE | An exact method for design exploration of quantum-dot cellular automata. | Marcel Walter, Robert Wille, Daniel Groe, Frank Sill Torres, Rolf Drechsler |
| 2018 | DDECS | Natural Language Based Power Domain Partitioning. | David Lemma, Daniel Groe, Rolf Drechsler |
| 2018 | DSD | Towards Reversed Approximate Hardware Design. | Saman Frhlich, Daniel Groe, Rolf Drechsler |
| 2018 | DSD | Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata. | Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Groe, Rolf Drechsler |
| 2018 | FDL | Extensible and Configurable RISC-V Based Virtual Prototype. | Vladimir Herdt, Daniel Groe, Hoang M. Le, Rolf Drechsler |
| 2018 | ICCAD | PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers. | Alireza Mahzoon, Daniel Groe, Rolf Drechsler |
| 2017 | ASPDAC | Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. | Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Groe, Rolf Drechsler |
| 2017 | DATE | Data flow testing for virtual prototypes. | Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Groe, Rolf Drechsler |
| 2017 | FDL | Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2017 | FDL | Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2017 | GECCO | An adaptive prioritized | Saeideh Shirinzadeh, Mathias Soeken, Daniel Groe, Rolf Drechsler |
| 2017 | ICCAD | Early SoC security validation by VP-based static information flow analysis. | Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2017 | MEMOCODE | Yise - a novel framework for boolean networks using y-inverter graphs. | Arun Chandrasekharan, Daniel Groe, Rolf Drechsler |
| 2016 | ASPDAC | BDD minimization for approximate computing. | Mathias Soeken, Daniel Groe, Arun Chandrasekharan, Rolf Drechsler |
| 2016 | CAV | ParCoSS: Efficient Parallelized Compiled Symbolic Simulation. | Vladimir Herdt, Hoang Minh Le, Daniel Groe, Rolf Drechsler |
| 2016 | DAC | Precise error determination of approximated components in sequential circuits with model checking. | Arun Chandrasekharan, Mathias Soeken, Daniel Groe, Rolf Drechsler |
| 2016 | DATE | Quantitative timing analysis of UML activity diagrams using statistical model checking. | Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Groe, Rolf Drechsler |
| 2016 | DATE | Towards formal verification of real-world SystemC TLM peripheral models - a case study. | Hoang Minh Le, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2016 | DATE | Formal verification of integer multipliers by combining Grbner basis with logic reduction. | Amr A. R. Sayed-Ahmed, Daniel Groe, Ulrich Khne, Mathias Soeken, Rolf Drechsler |
| 2016 | FDL | On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2016 | FMCAD | Equivalence checking using Grbner bases. | Amr A. R. Sayed-Ahmed, Daniel Groe, Mathias Soeken, Rolf Drechsler |
| 2016 | GECCO | Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. | Saeideh Shirinzadeh, Mathias Soeken, Daniel Groe, Rolf Drechsler |
| 2016 | ICCAD | Approximation-aware rewriting of AIGs for error tolerant applications. | Arun Chandrasekharan, Mathias Soeken, Daniel Groe, Rolf Drechsler |
| 2016 | ICCAD | Compiled symbolic simulation for systemC. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2016 | ICCD | Guided lightweight Software test qualification for IP integration using Virtual Prototypes. | Daniel Groe, Hoang M. Le, Muhammad Hassan, Rolf Drechsler |
| 2015 | ATVA | Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules. | Vladimir Herdt, Hoang Minh Le, Daniel Groe, Rolf Drechsler |
| 2014 | ASPDAC | Constraint-based platform variants specification for early system verification. | Andreas Burger, Alexander Viehl, Andreas Braun, Finn Haedicke, Daniel Groe, Oliver Bringmann, Wolfgang Rosenstiel |
| 2013 | DAC | Verifying SystemC using an intermediate verification language and symbolic simulation. | Hoang Minh Le, Daniel Groe, Vladimir Herdt, Rolf Drechsler |
| 2013 | DATE | Scalable fault localization for SystemC TLM designs. | Hoang Minh Le, Daniel Groe, Rolf Drechsler |
| 2013 | DSD | Minimal Stimuli Generation in Simulation-Based Verification. | Shuo Yang, Robert Wille, Daniel Groe, Rolf Drechsler |
| 2013 | ICSE | Towards automatic scenario generation from coverage information. | Melanie Diepenbeck, Mathias Soeken, Daniel Groe, Rolf Drechsler |
| 2012 | DATE | A guiding coverage metric for formal verification. | Finn Haedicke, Daniel Groe, Rolf Drechsler |
| 2012 | DSD | Coverage-Driven Stimuli Generation. | Shuo Yang, Robert Wille, Daniel Groe, Rolf Drechsler |
| 2012 | FDL | Localizing features of ESL models for design understanding. | Marc Michael, Daniel Groe, Rolf Drechsler |
| 2011 | DDECS | TLM protocol compliance checking at the Electronic System Level. | Mohamed Bawadekji, Daniel Groe, Rolf Drechsler |
| 2011 | FDL | Analyzing dependability measures at the Electronic System Level. | Marc Michael, Daniel Groe, Rolf Drechsler |
| 2011 | FMCAD | metaSMT: Focus on Your Application not on Solver Integration. | Finn Haedicke, Stefan Frehse, Grschwin Fey, Daniel Groe, Rolf Drechsler |
| 2011 | ISORC | Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines. | Kim Grttner, Andreas Herrholz, Ulrich Khne, Daniel Groe, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler |
| 2010 | MEMOCODE | Proving transaction and system-level properties of untimed SystemC TLM designs. | Daniel Groe, Hoang Minh Le, Rolf Drechsler |
| 2009 | DATE | Property analysis and design understanding. | Ulrich Khne, Daniel Groe, Rolf Drechsler |
| 2009 | DATE | Debugging of Toffoli networks. | Robert Wille, Daniel Groe, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
| 2009 | FDL | SMT-based stimuli generation in the SystemC Verification library. | Robert Wille, Daniel Groe, Finn Haedicke, Rolf Drechsler |
| 2009 | VLSID | Reversible Logic Synthesis with Output Permutation. | Robert Wille, Daniel Groe, Gerhard W. Dueck, Rolf Drechsler |
| 2009 | RSP | WoLFram- A Word Level Framework for Formal Verification. | Andr Slflow, Ulrich Khne, Grschwin Fey, Daniel Groe, Rolf Drechsler |
| 2008 | DATE | Quantified Synthesis of Reversible Logic. | Robert Wille, Hoang Minh Le, Gerhard W. Dueck, Daniel Groe |
| 2008 | FDL | Contradiction Analysis for Constraint-based Random Simulation. | Daniel Groe, Robert Wille, Robert Siegmund, Rolf Drechsler |
| 2008 | FDL | Debugging Contradictory Constraints in Constraint-Based Random Simulation. | Daniel Groe, Robert Wille, Robert Siegmund, Rolf Drechsler |
| 2007 | DATE | Estimating functional coverage in bounded model checking. | Daniel Groe, Ulrich Khne, Rolf Drechsler |
| 2007 | FDL | Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. | Daniel Groe, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler |
| 2007 | ICCAD | Fast exact Toffoli network synthesis of reversible logic. | Robert Wille, Daniel Groe |
| 2006 | DATE | Avoiding false negatives in formal verification for protocol-driven blocks. | Grschwin Fey, Daniel Groe, Rolf Drechsler |
| 2005 | GI | Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. | Daniel Groe, Ulrich Khne, Rolf Drechsler |
| 2005 | ISCAS | CheckSyC: an efficient property checker for RTL SystemC designs. | Daniel Groe, Rolf Drechsler |
| 2005 | RSP | SyCE: An Integrated Environment for System Design in SystemC. | Rolf Drechsler, Grschwin Fey, Christian Genz, Daniel Groe |
| 2004 | MEMOCODE | Checkers for SystemC designs. | Daniel Groe, Rolf Drechsler |
| 2003 | FDL | Efficient Automatic Visualization of SystemC Designs. | Daniel Groe, Rolf Drechsler, Lothar Linhard, Gerhard Angst |
| 2003 | ISCAS | Formal verification of LTL formulas for SystemC designs. | Daniel Groe, Rolf Drechsler |
| 2002 | DSD | Reachability Analysis for Formal Verification of SystemC. | Rolf Drechsler, Daniel Groe |
| 2001 | EUROGP | Heuristic Learning Based on Genetic Programming. | Nicole Drechsler, Frank Schmiedle, Daniel Groe, Rolf Drechsler |