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Forum on Specification and Design Languages

FDL

C

CORE rank

CORE rank (raw)

C

Fields of research

Software Engineering

Papers indexed

774

2003–2025

Papers per year

200371 peak2025

FDL papers

774 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2012Configurable load emulation using FPGA and power amplifiers for automotive power ICs.Manuel Harrant, Thomas Nirmaier, Georg Pelz, Fabrizio Dona, Christoph Grimm
2012Configurable Load Emulation Using FPGA and Power Amplifiers for Automotive Power ICs.Manuel Harrant, Thomas Nirmaier, Christoph Grimm, Georg Pelz
2012TLM POWER3: Power Estimation Methodology for SystemC TLM 2.0.David J. Greaves, Muhammad Mehboob Yasin
2012TLM POWER3: Power estimation methodology for SystemC TLM 2.0.David J. Greaves, Muhammad Mehboob Yasin
2012Transformation of event-driven HDL blocks for native integration into time-driven system models.Ralph Grgen, Jan-Hendrik Oetjens, Wolfgang Nebel
2012Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures.Johann Glaser, Clifford Wolf
2012Invasive computing with iOMP.Michael Gerndt, Andreas Hollmann, Marcel Meyer, Martin Schreiber, Josef Weidendorfer
2012An integrated simulation framework for invasive computing.Michael Gerndt, Frank Hannig, Andreas Herkersdorf, Andreas Hollmann, Marcel Meyer, Sascha Roloff, Josef Weidendorfer, Thomas Wild, Aurang Zaib
2012Formal Specification Level.Rolf Drechsler, Mathias Soeken, Robert Wille
2012Formal Specification Level: Towards verification-driven design based on natural language processing.Rolf Drechsler, Mathias Soeken, Robert Wille
2012Model-based progressive design and verification of an integrated CMOS magnetic sensor for automotive applications.Gael F. Close, Gjalt de Jong
2012Integrating virtual platforms into a heterogeneous MoC-based modeling framework.Gilmar S. Beserra, Seyed-Hosein Attarzadeh-Niaki, Ingo Sander
2012Formal Plausibility Checks for Environment Constraints.Binghao Bao, Jrg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2012Formal plausibility checks for environment constraints.Binghao Bao, Jrg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz
2012Efficient Refinement Strategy Exploiting Component Properties in a CEGAR Process.Syed Hussein Syed Alwi, Ccile Braunstein, Emmanuelle Encrenaz
2012An efficient refinement strategy exploiting component properties in a cegar process.Syed Hussein Syed Alwi, Ccile Braunstein, Emmanuelle Encrenaz
2012FAst optimization of analog amplifier architecture using simulated annealing.Sumit Adhikari, Florian Schupfer, Christoph Grimm
2011Systemc-AMS model of a dynamic large-scale satellite-based AIS-like network.Mu Zhou, Ren van Leuken
2011Designing low-power wireless sensor networks.Joseph Wenninger, Javier Moreno, Jan Haase, Christoph Grimm
2011VHDL-AMS model of a dual gate graphene FET.Ime J. Umoh, Tom J. Kazmierski
2011ESL power and performance estimation for heterogeneous MPSOCS using SystemC.Martin Streubhr, Rafael Rosales, Ralph Hasholzner, Christian Haubelt, Jrgen Teich
2011Bringing C++ productivity to VHDL world: From language definition to a case study.Ivan Shcherbakov, Christian Weis, Norbert Wehn
2011Assertion support in high-level synthesis design flow.Aurlien Ribon, Bertrand Le Gal, Christophe Jgo, Dominique Dallet
2011Does asynchronous technology bring robustness in synchronous circuit monitoring?Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet, Alejandro Chagoya
2011Impact simulation of changes to development processes: An ESL case study.Frank Poppen, Roland Koppe, Kim Grttner, Axel Hahn
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