International Symposium on High Performance Computer Architecture
HPCA
A*
CORE rank
CORE rank (raw)
A*
Fields of research
Computer Systems Engineering · Distributed Computing and Systems Software
Papers indexed
1,671
1995–2026
Papers per year
1995122 peak2026
Most published authors
HPCA papers
1,671 records sourced from DBLP. Search titles, filter by year, sort by recency.
| Year | Title | Authors |
|---|---|---|
| 2018 | Analyzing Topology Parameters for Achieving Energy-Efficient k-ary n-cubes. | Francisco J. Andujar, Salvador Coll, Marina Alonso, Juan-Miguel Martnez, Pedro Lpez, Francisco J. Alfaro, Jos L. Snchez, Ral Martnez |
| 2018 | Routerless Network-on-Chip. | Fawaz Alazemi, Arash AziziMazreah, Bella Bose, Lizhong Chen |
| 2017 | Camouflage: Memory Traffic Shaping to Mitigate Timing Attacks. | Yanqi Zhou, Sameer Wagh, Prateek Mittal, David Wentzlaff |
| 2017 | Balancing Performance and Lifetime of MLC PCM by Using a Region Retention Monitor. | Mingzhe Zhang, Lunkai Zhang, Lei Jiang, Zhiyong Liu, Frederic T. Chong |
| 2017 | Early Experiences with Saving Energy in Direct Interconnection Networks. | Felix Zahn, Steffen Lammel, Holger Frning |
| 2017 | Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors. | Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Reetuparna Das, Todd M. Austin |
| 2017 | An Effective Queuing Scheme to Provide Slim Fly Topologies with HoL Blocking Reduction and Deadlock Freedom for Minimal-Path Routing. | Pedro Ybenes, Jess Escudero-Sahuquillo, Pedro Javier Garca, Francisco J. Quiles, Torsten Hoefler |
| 2017 | Processing-in-Memory Enabled Graphics Processors for 3D Rendering. | Chenhao Xie, Shuaiwen Leon Song, Jing Wang, Weigong Zhang, Xin Fu |
| 2017 | Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links. | Sebastian Werner, Javier Navaridas, Mikel Lujn |
| 2017 | Cooperative Path-ORAM for Effective Memory Bandwidth Sharing in Server Settings. | Rujia Wang, Youtao Zhang, Jun Yang |
| 2017 | Secure Dynamic Memory Scheduling Against Timing Channel Attacks. | Yao Wang, Benjamin Wu, G. Edward Suh |
| 2017 | SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum Hardware Support. | Xiaodong Wang, Shuang Chen, Jeff Setter, Jos F. Martnez |
| 2017 | Design and Analysis of an APU for Exascale Computing. | Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan |
| 2017 | Controlled Kernel Launch for Dynamic Parallelism in GPUs. | Xulong Tang, Ashutosh Pattnaik, Huaipan Jiang, Onur Kayiran, Adwait Jog, Sreepathi Pai, Mohamed Assem Ibrahim, Mahmut T. Kandemir, Chita R. Das |
| 2017 | BRAVO: Balanced Reliability-Aware Voltage Optimization. | Karthik Swaminathan, Nandhini Chandramoorthy, Chen-Yong Cher, Ramon Bertran, Alper Buyuktosunoglu, Pradip Bose |
| 2017 | PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning. | Linghao Song, Xuehai Qian, Hai Li, Yiran Chen |
| 2017 | Towards Pervasive and User Satisfactory CNN across GPU Microarchitectures. | Mingcong Song, Yang Hu, Huixiang Chen, Tao Li |
| 2017 | Tiny Directory: Efficient Shared Memory in Many-Core Systems with Ultra-Low-Overhead Coherence Tracking. | Sudhanshu Shukla, Mainak Chaudhuri |
| 2017 | Dragonfly+: Low Cost Topology for Scaling Datacenters. | Alexander Shpiner, Zachy Haramaty, Saar Eliad, Vladimir Zdornov, Barak Gafni, Eitan Zahavi |
| 2017 | Knapp: A Packet Processing Framework for Manycore Accelerators. | Junhyun Shim, Joongi Kim, Keunhong Lee, Sue B. Moon |
| 2017 | A Split Cache Hierarchy for Enabling Data-Oriented Optimizations. | Andreas Sembrant, Erik Hagersten, David Black-Schaffer |
| 2017 | SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization. | Jee Ho Ryoo, Mitesh R. Meswani, Andreas Prodromou, Lizy K. John |
| 2017 | SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures. | Yuhwan Ro, Hyunyoon Cho, Eojin Lee, Daejin Jung, Young Hoon Son, Jung Ho Ahn, Jae W. Lee |
| 2017 | Efficient Sequential Consistency in GPUs via Relativistic Cache Coherence. | Xiaowei Ren, Mieszko Lis |
| 2017 | Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices. | Karthik Rao, Jun Wang, Sudhakar Yalamanchili, Yorai Wardi, Handong Ye |
751–775 of 1,671← PreviousNext →
Comparable venues
Other A*/A conferences filed under the same field of research.
- ADATEDesign, Automation and Test in Europe Conference
- A*DACDesign Automation Conf
- ASCInternational Conference for High Performance Computing, Networking, Storage and Analysis (was Supercomputing Conference)
- AICCADIEEE/ACM International Conference on Computer-Aided Design
- AITCIEEE International Test Conference
- A*ISCAACM International Symposium on Computer Architecture
- A*MICROInternational Symposium on Microarchitecture
- AISLPEDIEEE/ACM International Symposium on Low Power Electronics and Design