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Nam Sung Kim

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

152

Venues

27

Active years

2002–2026

Best venue rank

A*

Where they publish

Papers

152 indexed papers, newest first.

YearVenueTitleAuthors
2026ASPLOSTiNA: Tiered Network Buffer Architecture for Fast Networking in Chiplet-based CPUs.Siddharth Agarwal, Tianchen Wang, Jinghan Huang, Saksham Agarwal, Nam Sung Kim
2026HPCAMemSOS: OS-Guided Selective Memory Mirroring.Junghoon Kim, Jongheon Jeong, Seokwon Moon, Seong Hoon Seo, Yeonhong Park, Jinkyu Jeong, Nam Sung Kim, Jae W. Lee
2026HPCALiLo: Harnessing the on-Chip Accelerators in Intel CPUs for Compressed LLM Inference Acceleration.Hyungyo Kim, Qirong Xia, Jinghan Huang, Nachuan Wang, Younjoo Lee, Jung Ho Ahn, Wajdi K. Feghali, Ren Wang, Nam Sung Kim
2026HPCAReScue: Reliable and Secure CXL Memory.Chihun Song, Austin Antony Cruz, Michael Jaemin Kim, Minbok Wi, Gaohan Ye, Kyungsan Kim, Sangyeol Lee, Jung Ho Ahn, Nam Sung Kim
2026ISCAPVAC: A Rowhammer Mitigation Architecture Exploiting Per-Victim-Row Counting.Jumin Kim, Seungmin Baek, Hwayong Nam, Minbok Wi, Nam Sung Kim, Jung Ho Ahn
2026ISPASSCompiler and System Optimizations for Gem5 Simulator.Haneul Park, Siddharth Agarwal, Pradyun Narkadamilli, Kiung Jung, Yongjun Park, Ipoom Jeong, Nam Sung Kim
2026SPSoK: Systematizing a Decade of Architectural Rowhammer Defenses Through the Lens of Streaming Algorithms.Michael Jaemin Kim, Seungmin Baek, Jumin Kim, Hwayong Nam, Nam Sung Kim, Jung Ho Ahn
2025ASPLOSMarionette: A RowHammer Attack via Row Coupling.Seungmin Baek, Minbok Wi, Seonyong Park, Hwayong Nam, Michael Jaemin Kim, Nam Sung Kim, Jung Ho Ahn
2025ASPLOSM5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems.Yan Sun, Jongyul Kim, Zeduo Yu, Jiyuan Zhang, Siyuan Chai, Michael Jaemin Kim, Hwayong Nam, Jaehyun Park, Eojin Na, Yifan Yuan, Ren Wang, Jung Ho Ahn, Tianyin Xu, Nam Sung Kim
2025DACA Full-system, Programmable, and Extensible In-Memory Computing Simulation Framework for Deep Learning.Kaining Zhou, Jian Huang, Nam Sung Kim, Naresh Shanbhag
2025HPCAWarped-Compaction: Maximizing GPU Register File Bandwidth Utilization via Operand Compaction.Eunbi Jeong, Ipoom Jeong, Myung Kuk Yoon, Nam Sung Kim
2025ISCAUPP: Universal Predicate Pushdown to Smart Storage.Ipoom Jeong, Jinghan Huang, Chuxuan Hu, Dohyun Park, Jaeyoung Kang, Nam Sung Kim, Yongjoo Park
2025ISCALIA: A Single-GPU LLM Inference Acceleration with Cooperative AMX-Enabled CPU-GPU Computation and CXL Offloading.Hyungyo Kim, Nachuan Wang, Qirong Xia, Jinghan Huang, Amir Yazdanbakhsh, Nam Sung Kim
2025ISCADynamic Load Balancer in Intel Xeon Scalable Processor: Performance Analyses, Enhancements, and Guidelines.Jiaqi Lou, Srikar Vanavasam, Yifan Yuan, Ren Wang, Nam Sung Kim
2025ISCAA4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices.Haneul Park, Jiaqi Lou, Sangjin Lee, Yifan Yuan, KyoungSoo Park, Yongseok Son, Ipoom Jeong, Nam Sung Kim
2025ISCAHybrid SLC-MLC RRAM Mixed-Signal Processing-in-Memory Architecture for Transformer Acceleration via Gradient Redistribution.Chang Eun Song, Priyansh Bhatnagar, Zihan Xia, Nam Sung Kim, Tajana Rosing, Mingu Kang
2025ISPASSIntel in-Memory Analytics Accelerator: Performance Characterization and Guidelines.Jaeyoung Kang, Qirong Xia, Ipoom Jeong, Yongjoo Park, Nam Sung Kim
2025MICRONetZIP: Algorithm/Hardware Co-design of In-network Lossless Compression for Distributed Large Model Training.Jinghan Huang, Hyungyo Kim, Nachuan Wang, Jaeyoung Kang, Hrishi Shah, Eun Kyung Lee, Minjia Zhang, Fan Lai, Nam Sung Kim
2025MICROStratum: System-Hardware Co-Design with Tiered Monolithic 3D-Stackable DRAM for Efficient MoE Serving.Yue Pan, Zihan Xia, Po-Kai Hsu, Lanxiang Hu, Hyungyo Kim, Janak Sharda, Minxuan Zhou, Nam Sung Kim, Shimeng Yu, Tajana Rosing, Mingu Kang
2025MICRODRAM Fault Classification through Large-Scale Field Monitoring for Robust Memory RAS Management.Hoiju Chung, Euisang Oh, Seungmin Baek, Hyeongshin Yoon, Jaesung Yoo, Sanghwan Lee, Yongjun Lee, Arhatha Bramhanand, Brett Dodds, Yang Zhou, Nam Sung Kim
2025MICRORe-architecting End-host Networking with CXL: Coherence, Memory, and Offloading.Houxiang Ji, Yifan Yuan, Yang Zhou, Ipoom Jeong, Ren Wang, Saksham Agarwal, Nam Sung Kim
2025USENIXPara-ksm: Parallelized Memory Deduplication with Data Streaming Accelerator.Houxiang Ji, Minho Kim, Seonmu Oh, Daehoon Kim, Nam Sung Kim
2024ASPLOSAttAcc! Unleashing the Power of PIM for Batched Transformer-based Generative Model Inference.Jaehyun Park, Jaewan Choi, Kwanhee Kyung, Michael Jaemin Kim, Yongsuk Kwon, Nam Sung Kim, Jung Ho Ahn
2024ASPLOSTandem Processor: Grappling with Emerging Operators in Neural Networks.Soroush Ghodrati, Sean Kinzer, Hanyang Xu, Rohan Mahapatra, Yoonsung Kim, Byung Hoon Ahn, Dong Kai Wang, Lavanya Karthikeyan, Amir Yazdanbakhsh, Jongse Park, Nam Sung Kim, Hadi Esmaeilzadeh
2024ASPLOSA Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors.Reese Kuper, Ipoom Jeong, Yifan Yuan, Ren Wang, Narayan Ranganathan, Nikhil Rao, Jiayu Hu, Sanjay Kumar, Philip Lantz, Nam Sung Kim
2024ASPLOSTAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks.Chihun Song, Michael Jaemin Kim, Tianchen Wang, Houxiang Ji, Jinghan Huang, Ipoom Jeong, Jaehyun Park, Hwayong Nam, Minbok Wi, Jung Ho Ahn, Nam Sung Kim
2024EuroSysScaleCache: A Scalable Page Cache for Multiple Solid-State Drives.Kiet Tuan Pham, Seokjoo Cho, Sangjin Lee, Lan Anh Nguyen, Hyeongi Yeo, Ipoom Jeong, Sungjin Lee, Nam Sung Kim, Yongseok Son
2024HPCAUnleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models.Jaewan Choi, Jaehyun Park, Kwanhee Kyung, Nam Sung Kim, Jung Ho Ahn
2024HPCASPADE: Sparse Pillar-based 3D Object Detection Accelerator for Autonomous Driving.Minjae Lee, Seongmin Park, Hyungmin Kim, Minyong Yoon, Janghwan Lee, Jun Won Choi, Nam Sung Kim, Mingu Kang, Jungwook Choi
2024HPCAAn LPDDR-based CXL-PNM Platform for TCO-efficient Inference of Transformer-based Large Language Models.Sangsoo Park, KyungSoo Kim, Jinin So, Jin Jung, Jonggeon Lee, Kyoungwan Woo, Nayeon Kim, Younghyun Lee, Hyungyo Kim, Yongsuk Kwon, Jinhyun Kim, Jieun Lee, YeonGon Cho, Yongmin Tai, Jeonghyeon Cho, Hoyoung Song, Jung Ho Ahn, Nam Sung Kim
2024ISCAHAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative Computing.Jinghan Huang, Jiaqi Lou, Srikar Vanavasam, Xinhao Kong, Houxiang Ji, Ipoom Jeong, Danyang Zhuo, Eun Kyung Lee, Nam Sung Kim
2024ISCADRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands.Hwayong Nam, Seungmin Baek, Minbok Wi, Michael Jaemin Kim, Jaehyun Park, Chihun Song, Nam Sung Kim, Jung Ho Ahn
2024ISCAIntel Accelerators Ecosystem: An SoC-Oriented Perspective : Industry Product.Yifan Yuan, Ren Wang, Narayan Ranganathan, Nikhil Rao, Sanjay Kumar, Philip Lantz, Vivekananthan Sanjeepan, Jorge Cabrera, Atul Kwatra, Rajesh Sankaran, Ipoom Jeong, Nam Sung Kim
2024MICRODemystifying a CXL Type-2 Device: A Heterogeneous Cooperative Computing Perspective.Houxiang Ji, Srikar Vanavasam, Yang Zhou, Qirong Xia, Jinghan Huang, Yifan Yuan, Ren Wang, Pekon Gupta, Bhushan Chitlur, Ipoom Jeong, Nam Sung Kim
2024NSDIHarmonic: Hardware-assisted RDMA Performance Isolation for Public Clouds.Jiaqi Lou, Xinhao Kong, Jinghan Huang, Wei Bai, Nam Sung Kim, Danyang Zhuo
2023HotOSTowards a Manageable Intra-Host Network.Xinhao Kong, Jiaqi Lou, Wei Bai, Nam Sung Kim, Danyang Zhuo
2023HPCASHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling.Minbok Wi, Jaehyun Park, Seoyoung Ko, Michael Jaemin Kim, Nam Sung Kim, Eojin Lee, Jung Ho Ahn
2023HPCARambda: RDMA-driven Acceleration Framework for Memory-intensive s-scale Datacenter Applications.Yifan Yuan, Jinghan Huang, Yan Sun, Tianchen Wang, Jacob Nelson, Dan R. K. Ports, Yipeng Wang, Ren Wang, Charlie Tai, Nam Sung Kim
2023ISCAMESA: Microarchitecture Extensions for Spatial Architecture Generation.Dong Kai Wang, Jiaqi Lou, Naiyin Jin, Edwin Mascarenhas, Rohan Mahapatra, Sean Kinzer, Soroush Ghodrati, Amir Yazdanbakhsh, Hadi Esmaeilzadeh, Nam Sung Kim
2023ISPASSAnalyzing Energy Efficiency of a Server with a SmartNIC under SLO Constraints.Jinghan Huang, Jiaqi Lou, Yan Sun, Tianchen Wang, Eun Kyung Lee, Nam Sung Kim
2023MICROHow to Kill the Second Bird with One ECC: The Pursuit of Row Hammer Resilient DRAM.Michael Jaemin Kim, Minbok Wi, Jaehyun Park, Seoyoung Ko, Jaeyoung Choi, Hwayong Nam, Nam Sung Kim, Jung Ho Ahn, Eojin Lee
2023MICRODemystifying CXL Memory with Genuine CXL-Ready Systems and Devices.Yan Sun, Yifan Yuan, Zeduo Yu, Reese Kuper, Chihun Song, Jinghan Huang, Houxiang Ji, Siddharth Agarwal, Jiaqi Lou, Ipoom Jeong, Ren Wang, Jung Ho Ahn, Tianyin Xu, Nam Sung Kim
2023USENIXSTYX: Exploiting SmartNIC Capability to Reduce Datacenter Memory Tax.Houxiang Ji, Mark Mansi, Yan Sun, Yifan Yuan, Jinghan Huang, Reese Kuper, Michael M. Swift, Nam Sung Kim
2022FPGAAn FPGA-based RNN-T Inference Accelerator with PIM-HBM.Shinhaeng Kang, Sukhan Lee, Byeongho Kim, Hweesoo Kim, Kyomin Sohn, Nam Sung Kim, Eojin Lee
2022ICLRPipeGCN: Efficient Full-Graph Training of Graph Convolutional Networks with Pipelined Feature Communication.Cheng Wan, Youjie Li, Cameron R. Wolfe, Anastasios Kyrillidis, Nam Sung Kim, Yingyan Lin
2022ISCAASAP: architecture support for asynchronous persistence.Ahmed H. M. O. Abulila, Izzat El Hajj, Myoungsoo Jung, Nam Sung Kim
2022MICROIDIO: Network-Driven, Inbound Network Data Orchestration on Server Processors.Mohammad Alian, Siddharth Agarwal, Jongmin Shin, Neel Patel, Yifan Yuan, Daehoon Kim, Ren Wang, Nam Sung Kim
2022NSDIUnlocking the Power of Inline Floating-Point Operations on Programmable Switches.Yifan Yuan, Omar Alama, Jiawei Fei, Jacob Nelson, Dan R. K. Ports, Amedeo Sapio, Marco Canini, Nam Sung Kim
2021ASPLOSDiAG: a dataflow-inspired architecture for general-purpose processors.Dong Kai Wang, Nam Sung Kim
2021HotOSDoing more with less: training large DNN models on commodity servers for the masses.Youjie Li, Amar Phanishayee, Derek Murray, Nam Sung Kim
2021HPCAQEI: Query Acceleration Can be Generic and Efficient in the Cloud.Yifan Yuan, Yipeng Wang, Ren Wang, Rangeen Basu Roy Chowdhury, Charlie Tai, Nam Sung Kim
2021ISCARevamping Storage Class Memory With Hardware Automated Memory-Over-Storage Solution.Jie Zhang, Miryeong Kwon, Donghyun Gouk, Sungjoon Koh, Nam Sung Kim, Mahmut Taylan Kandemir, Myoungsoo Jung
2021ISCAHardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product.Sukhan Lee, Shinhaeng Kang, Jaehoon Lee, Hyeonsu Kim, Eojin Lee, Seungwoo Seo, Hosang Yoon, Seungwon Lee, Kyounghwan Lim, Hyunsung Shin, Jinhyun Kim, Seongil O, Anand Iyer, David Wang, Kyomin Sohn, Nam Sung Kim
2021ISCADon't Forget the I/O When Allocating Your LLC.Yifan Yuan, Mohammad Alian, Yipeng Wang, Ren Wang, Ilia Kurakin, Charlie Tai, Nam Sung Kim
2021MICRONMAP: Power Management Based on Network Packet Processing Mode Transition for Latency-Critical Workloads.Ki-Dong Kang, Gyeongseo Park, Hyosang Kim, Mohammad Alian, Nam Sung Kim, Daehoon Kim
2021MICROGreenDIMM: OS-assisted DRAM Power Management for DRAM with a Sub-array Granularity Power-Down State.Seunghak Lee, Ki-Dong Kang, Hwanjun Lee, Hyungwon Park, Young Hoon Son, Nam Sung Kim, Daehoon Kim
2020DACBit-Parallel Vector Composability for Neural Acceleration.Soroush Ghodrati, Hardik Sharma, Cliff Young, Nam Sung Kim, Hadi Esmaeilzadeh
2020ISCABabelFish: Fusing Address Translations for Containers.Dimitrios Skarlatos, Umur Darbaz, Bhargava Gopireddy, Nam Sung Kim, Josep Torrellas
2020ISPASSData Direct I/O Characterization for Future I/O System Exploration.Mohammad Alian, Yifan Yuan, Jie Zhang, Ren Wang, Myoungsoo Jung, Nam Sung Kim
2020MICROFReaC Cache: Folded-logic Reconfigurable Computing in the Last Level Cache.Ashutosh Dhar, Xiaohao Wang, Hubertus Franke, Jinjun Xiong, Jian Huang, Wen-Mei W. Hwu, Nam Sung Kim, Deming Chen
2020MICROPlanaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks.Soroush Ghodrati, Byung Hoon Ahn, Joon Kyung Kim, Sean Kinzer, Brahmendra Reddy Yatham, Navateja Alla, Hardik Sharma, Mohammad Alian, Eiman Ebrahimi, Nam Sung Kim, Cliff Young, Hadi Esmaeilzadeh
2020VLSIDLeveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task Scheduling.Ashutosh Dhar, Mang Yu, Wei Zuo, Xiaohao Wang, Nam Sung Kim, Deming Chen
2019ASPLOSFlatFlash: Exploiting the Byte-Accessibility of SSDs within a Unified Memory-Storage Hierarchy.Ahmed H. M. O. Abulila, Vikram Sharma Mailthody, Zaid Qureshi, Jian Huang, Nam Sung Kim, Jinjun Xiong, Wen-Mei W. Hwu
2019DACPractical Near-Data Processing to Evolve Memory and Storage Devices into Mainstream Heterogeneous Computing Systems.Nam Sung Kim, Pankaj Mehra
2019DACLL-PCM: Low-Latency Phase Change Memory Architecture.Nam Sung Kim, Choungki Song, Woo Young Cho, Jian Huang, Myoungsoo Jung
2019ISCAAxMemo: hardware-compiler co-design for approximate code memoization.Zhenhong Liu, Amir Yazdanbakhsh, Dong Kai Wang, Hadi Esmaeilzadeh, Nam Sung Kim
2019ISLPEDADong Kai Wang, Nam Sung Kim
2019MICRONetDIMM: Low-Latency Near-Memory Network Interface Architecture.Mohammad Alian, Nam Sung Kim
2018CLOUDVIP: Virtual Performance-State for Efficient Power Management of Virtual Machines.Ki-Dong Kang, Mohammad Alian, Daehoon Kim, Jaehyuk Huh, Nam Sung Kim
2018FCCMFlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial Networks.Amir Yazdanbakhsh, Michael Brzozowski, Behnam Khaleghi, Soroush Ghodrati, Kambiz Samadi, Nam Sung Kim, Hadi Esmaeilzadeh
2018ISCAPROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms.Prakalp Srivastava, Mingu Kang, Sujan K. Gonugondla, Sungmin Lim, Jungwook Choi, Vikram S. Adve, Nam Sung Kim, Naresh R. Shanbhag
2018ISCAGANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial Networks.Amir Yazdanbakhsh, Kambiz Samadi, Nam Sung Kim, Hadi Esmaeilzadeh
2018ISLPEDLoad-Triggered Warp Approximation on GPU.Zhenhong Liu, Daniel Wong, Nam Sung Kim
2018MICROApplication-Transparent Near-Memory Processing Architecture with Memory Channel Network.Mohammad Alian, Seungwon Min, Hadi Asgharimoghaddam, Ashutosh Dhar, Dong Kai Wang, Thomas Roewer, Adam J. McPadden, Oliver O'Halloran, Deming Chen, Jinjun Xiong, Daehoon Kim, Wen-Mei W. Hwu, Nam Sung Kim
2018MICROAmber*: Enabling Precise Full-System Simulation with Detailed Modeling of All SSD Resources.Donghyun Gouk, Miryeong Kwon, Jie Zhang, Sungjoon Koh, Wonil Choi, Nam Sung Kim, Mahmut T. Kandemir, Myoungsoo Jung
2018MICROA Network-Centric Hardware/Algorithm Co-Design to Accelerate Distributed Training of Deep Neural Networks.Youjie Li, Jongse Park, Mohammad Alian, Yifan Yuan, Zheng Qu, Peitian Pan, Ren Wang, Alexander G. Schwing, Hadi Esmaeilzadeh, Nam Sung Kim
2018OSDIFlashShare: Punching Through Server Storage Stack from Kernel to Firmware for Ultra-Low Latency SSDs.Jie Zhang, Miryeong Kwon, Donghyun Gouk, Sungjoon Koh, Changlim Lee, Mohammad Alian, Myoungjun Chun, Mahmut Taylan Kandemir, Nam Sung Kim, Jihong Kim, Myoungsoo Jung
2017CLOUDJanus: supporting heterogeneous power management in virtualized environments.Daehoon Kim, Mohammad Alian, Jaehyuk Huh, Nam Sung Kim
2017HPCANCAP: Network-Driven, Packet Context-Aware Power Management for Client-Server Architecture.Mohammad Alian, Ahmed H. M. O. Abulila, Lokesh Jindal, Daehoon Kim, Nam Sung Kim
2017HPCADefect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices.Sang-uhn Cha, Seongil O, Hyunsung Shin, Sangjoon Hwang, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Gyo-Young Jin, Young Hoon Son, Hyunyoon Cho, Jung Ho Ahn, Nam Sung Kim
2017HPCAG-Scalar: Cost-Effective Generalized Scalar Execution Architecture for Power-Efficient GPUs.Zhenhong Liu, Syed Zohaib Gilani, Murali Annavaram, Nam Sung Kim
2017ISLPEDTemporal codes in on-chip interconnects.Michael Mishkin, Nam Sung Kim, Mikko H. Lipasti
2017ISPASSdist-gem5: Distributed simulation of computer clusters.Mohammad Alian, Umur Darbaz, Gbor Dzsa, Stephan Diestelhorst, Daehoon Kim, Nam Sung Kim
2017MICROPageforge: a near-memory content-aware page-merging architecture.Dimitrios Skarlatos, Nam Sung Kim, Josep Torrellas
2016DACVR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency.Hadi Asghari Moghaddam, Hamid Reza Ghasemi, Abhishek Arvind Sinkar, Indrani Paul, Nam Sung Kim
2016HPCAApproximating warps with intra-warp operand value similarity.Daniel Wong, Nam Sung Kim, Murali Annavaram
2016HPCAScalCore: Designing a core for voltage scalability.Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal, Asit K. Mishra
2016HPCADUANG: Fast and lightweight page migration in asymmetric memory systems.Hao Wang, Jie Zhang, Sharmila Shridhar, Gieseo Park, Myoungsoo Jung, Nam Sung Kim
2016ICCDVARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches.S. Karen Khatamifard, Michael Resch, Nam Sung Kim, Ulya R. Karpuzcu
2016ICCDCNFET-based high throughput register file architecture.Tianjian Li, Li Jiang, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang
2016ISLPEDBit Serializing a Microprocessor for Ultra-low-power.Matthew Tomei, Henry Duwe, Nam Sung Kim, Rakesh Kumar
2016ISLPEDOn Effective and Efficient Quality Management for Approximate Computing.Ting Wang, Qian Zhang, Nam Sung Kim, Qiang Xu
2016MICROChameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems.Hadi Asghari Moghaddam, Young Hoon Son, Jung Ho Ahn, Nam Sung Kim
2016MICROSnatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks.Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert C. N. Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas
2015HPCANDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules.Amin Farmahini Farahani, Jung Ho Ahn, Katherine Morrow, Nam Sung Kim
2015HPCAiPatch: Intelligent fault patching to improve energy efficiency.David J. Palframan, Nam Sung Kim, Mikko H. Lipasti
2015HPCACiDRA: A cache-inspired DRAM resilience architecture.Young Hoon Son, Sukhan Lee, Seongil O, Sanghyuk Kwon, Nam Sung Kim, Jung Ho Ahn
2015HPCAAlloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems.Hao Wang, Chang-Jae Park, Gyungsu Byun, Jung Ho Ahn, Nam Sung Kim
2015ICCDComparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications.Hamid Reza Ghasemi, Ulya R. Karpuzcu, Nam Sung Kim
2015ISCACOP: to compress and protect main memory.David J. Palframan, Nam Sung Kim, Mikko H. Lipasti
2015MICROGPU register file virtualization.Hyeran Jeon, Gokul Subramanian Ravi, Nam Sung Kim, Murali Annavaram
2015MICROvCache: architectural support for transparent and isolated virtual LLCs in virtualized environments.Daehoon Kim, Hwanju Kim, Nam Sung Kim, Jaehyuk Huh
2015USENIXBolt: Faster Reconfiguration in Operating Systems.Sankaralingam Panneerselvam, Michael M. Swift, Nam Sung Kim
2014ASPDACQoS-aware dynamic resource allocation for spatial-multitasking GPUs.Paula Aguilera, Katherine Morrow, Nam Sung Kim
2014DATEProcess variation-aware workload partitioning algorithms for GPUs supporting spatial-multitasking.Paula Aguilera, Jungseob Lee, Amin Farmahini Farahani, Katherine Morrow, Michael J. Schulte, Nam Sung Kim
2014HPCAAccordion: Toward soft Near-Threshold Voltage Computing.Ulya R. Karpuzcu, Ismail Akturk, Nam Sung Kim
2014HPCAPrecision-aware soft error protection for GPUs.David J. Palframan, Nam Sung Kim, Mikko H. Lipasti
2014ICCDFair share: Allocation of GPU resources for both performance and fairness.Paula Aguilera, Katherine Morrow, Nam Sung Kim
2014ISCASleepScale: Runtime joint speed scaling and sleep states management for power efficient data centers.Yanpei Liu, Stark C. Draper, Nam Sung Kim
2014ISCARow-buffer decoupling: A case for low-latency DRAM microarchitecture.Seongil O, Young Hoon Son, Nam Sung Kim, Jung Ho Ahn
2014ISCASQuantitative comparison of the power reduction techniques for samsung reconfigurable processor.Hoyoung Kim, Soojung Ryu, Abhishek A. Sinkar, Nam Sung Kim
2014ISPASSEnergy-efficient reconfigurable cache architectures for accelerator-enabled embedded systems.Amin Farmahini Farahani, Nam Sung Kim, Katherine Morrow
2013ASPDACReevaluating the latency claims of 3D stacked memories.Daniel W. Chang, Gyungsu Byun, Hoyoung Kim, Minwook Ahn, Soojung Ryu, Nam Sung Kim, Michael J. Schulte
2013HPCAPower-efficient computing for compute-intensive GPGPU applications.Syed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte
2013HPCAEnergySmart: Toward energy-efficient manycores for Near-Threshold Computing.Ulya R. Karpuzcu, Abhishek A. Sinkar, Nam Sung Kim, Josep Torrellas
2013ICCADDynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os.Daniel W. Chang, Young Hoon Son, Jung Ho Ahn, Hoyoung Kim, Minwook Ahn, Michael J. Schulte, Nam Sung Kim
2013ICCADImproving platform energy: chip area trade-off in near-threshold computing environment.Hao Wang, Abhishek A. Sinkar, Nam Sung Kim
2013ISCAGPUWattch: enabling energy optimizations in GPGPUs.Jingwen Leng, Tayler H. Hetherington, Ahmed ElTantawy, Syed Zohaib Gilani, Nam Sung Kim, Tor M. Aamodt, Vijay Janapa Reddi
2013ISLPEDREEL: Reducing effective execution latency of floating point operations.Vignyan Reddy, Syed Zohaib Gilani, Erika Gunadi, Nam Sung Kim, Michael J. Schulte, Mikko H. Lipasti
2013MICROExploiting GPU peak-power and performance tradeoffs through reduced effective pipeline latency.Syed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte
2012DACCost-effective power delivery to support per-core voltage domains for power-constrained processors.Hamid Reza Ghasemi, Abhishek A. Sinkar, Michael J. Schulte, Nam Sung Kim
2012DATEWorkload-aware voltage regulator optimization for power efficient multi-core processors.Abhishek A. Sinkar, Hao Wang, Nam Sung Kim
2012DSNVARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages.Ulya R. Karpuzcu, Krishna B. Kolluru, Nam Sung Kim, Josep Torrellas
2012DSNMitigating random variation with spare RIBs: Redundant intermediate bitslices.David J. Palframan, Nam Sung Kim, Mikko H. Lipasti
2012HPCAThe case for GPGPU spatial multitasking.Jacob Adriaens, Katherine Compton, Nam Sung Kim, Michael J. Schulte
2011ACSSCEnergy-efficient floating-point arithmetic for digital signal processors.Syed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte
2011ASPDACAVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors.Abhishek A. Sinkar, Nam Sung Kim
2011DATEScratchpad memory optimizations for digital signal processing applications.Syed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte
2011DATETime redundant parity for low-cost transient error detection.David J. Palframan, Nam Sung Kim, Mikko H. Lipasti
2011HPCALow-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors.Hamid Reza Ghasemi, Stark C. Draper, Nam Sung Kim
2011ISPASSAnalyzing throughput of GPGPUs exploiting within-die core-to-core frequency variation.Jungseob Lee, Paritosh Pratap Ajgaonkar, Nam Sung Kim
2010ASPDACAnalyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processors.Jungseob Lee, Shi-Ting Zhou, Nam Sung Kim
2010ASPDACRuntime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors.Dongkeun Oh, Nam Sung Kim, Charlie Chung-Ping Chen, Azadeh Davoodi, Yu Hen Hu
2010ICCADOptimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors.Danbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim
2010ICCDMinimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC.Shi-Ting Zhou, Sumeet Katariya, Hamid Reza Ghasemi, Stark C. Draper, Nam Sung Kim
2010ISLPEDWorkload-adaptive process tuning strategy for power-efficient multi-core processors.Jungseob Lee, Chi-Chao Wang, Hamid Reza Ghasemi, Lloyd Bircher, Yu Cao, Nam Sung Kim
2010MICROCombating Aging with the Colt Duty Cycle Equalizer.Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mikko H. Lipasti
2009DACOptimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating.Jungseob Lee, Nam Sung Kim
2009ISLPEDStatistical static timing analysis considering leakage variability in power gated designs.Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek A. Sinkar, Nam Sung Kim
2009ISLPEDFrequency and yield optimization using power gates in power-constrained designs.Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin
2009ISLPEDOptimizing total power of many-core processors considering voltage scaling limit and process variations.Jungseob Lee, Nam Sung Kim
2009ISLPEDAnalyzing potential power reduction with adaptive voltage positioning optimized for multicore processors.Abhishek A. Sinkar, Nam Sung Kim
2007DSDOn-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology.David Roberts, Nam Sung Kim, Trevor N. Mudge
2007ICCADYield-driven near-threshold SRAM design.Gregory K. Chen, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim
2005DATEPower-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage.Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge
2004ISLPEDMicroarchitectural power modeling techniques for deep sub-micron microprocessors.Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge
2003ICCADLeakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches.Nam Sung Kim, David T. Blaauw, Trevor N. Mudge
2003ICSReducing register ports using delayed write-back queues and operand pre-fetch.Nam Sung Kim, Trevor N. Mudge
2003ISLPEDThe microarchitecture of a low power register file.Nam Sung Kim, Trevor N. Mudge
2003MICRORazor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation.Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David T. Blaauw, Todd M. Austin, Krisztin Flautner, Trevor N. Mudge
2002ISCADrowsy Caches: Simple Techniques for Reducing Leakage Power.Krisztin Flautner, Nam Sung Kim, Steven M. Martin, David T. Blaauw, Trevor N. Mudge
2002MICRODrowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction.Nam Sung Kim, Krisztin Flautner, David T. Blaauw, Trevor N. Mudge